[A-2] Threshold Voltage Control | 2025 International Conference on Solid State Devices and Materials

Advanced Search

Session Details

Oral Presentation01: Advanced CMOS: Material Science / Process Engineering / Device Technology

[A-2]Threshold Voltage Control

Tue. Sep 16, 2025 3:30 PM - 5:00 PM JST
Tue. Sep 16, 2025 6:30 AM - 8:00 AM UTC

Room A (301, 3rd Floor)

Session Chair: Keisuke Yamamoto (Kumamoto Univ.), Genji Nakamura (Tokyo Electron Ltd.)

3:30 PM - 3:45 PM JST(6:30 AM - 6:45 AM UTC)

[A-2-01]Vt Fine-Tuning for Multi-Vt using Wet Fine-Etching of LaO in Dipole-first

〇Hikaru Kawarazaki¹, Ju-Geng Lai⁴, Hiroaki Arimura⁴, Leo Lukose⁴, Dai Ueda¹, Stephan Brus⁴, Yukifumi Yoshida², Takayoshi Tanaka², Yoichi Tanaka³, Koji Nakata³, Yuuichi Ogawa³, Nobuko Gan³, Hideaki Iino³, Min-Soo Kim⁴, Naoto Horiguchi⁴, Naveen Reddy⁴, Efrain Altamirano Sanchez⁴ (1. SCREEN SPE Germany GmbH (Germany), 2. SCREEN Semiconductor Solutions Co., Ltd. (Japan), 3. Kurita Water Industries Ltd. (Japan), 4. imec (Belgium))

3:45 PM - 4:00 PM JST(6:45 AM - 7:00 AM UTC)

[A-2-02]Fluorine-Compatible Dipole-First Gate Stack

〇Sangkuk Han¹, Kyungsoo Park¹, Wonjae Choi¹, Wonyoung Jang¹, Haesoo Jang¹, Kyungwook Park¹, Changhwan Choi¹ (1. Hanyang university (Korea))

4:00 PM - 4:15 PM JST(7:00 AM - 7:15 AM UTC)

[A-2-03]Threshold Voltage Design for GAAFETs through Work Function Metal Thickness Engineering under Tight Nanosheet Spacing

〇Hiroyuki Ota¹, Yukinori Morita¹, Kenzo Manabe¹, Misako Morota¹, Naoya Okada¹, Shinji Migita¹, Yoshihiro Hayashi¹ (1. AIST (Japan))

4:15 PM - 4:30 PM JST(7:15 AM - 7:30 AM UTC)

2025 International Conference on Solid State Devices and Materials

Session Details

[A-2]Threshold Voltage Control

[A-2-01]Vt Fine-Tuning for Multi-Vt using Wet Fine-Etching of LaO in Dipole-first

[A-2-02]Fluorine-Compatible Dipole-First Gate Stack

[A-2-03]Threshold Voltage Design for GAAFETs through Work Function Metal Thickness Engineering under Tight Nanosheet Spacing

[A-2-04]Density Functional Theory Analysis of V_t and CMOS Polarity Control in Si High K based FETs

[A-2-05]Mechanism of Fluorine-induced Suppression of Effective Work Function Lowering in TiN/TiAlC Metal Gate Electrodes

[A-2-06]Flat-Band Voltage Tuning through Al Layer Position Engineering

Session Details

[A-2]Threshold Voltage Control

[A-2-01]Vt Fine-Tuning for Multi-Vt using Wet Fine-Etching of LaO in Dipole-first

[A-2-02]Fluorine-Compatible Dipole-First Gate Stack

[A-2-03]Threshold Voltage Design for GAAFETs through Work Function Metal Thickness Engineering under Tight Nanosheet Spacing

[A-2-04]Density Functional Theory Analysis of Vt and CMOS Polarity Control in Si High K based FETs

[A-2-05]Mechanism of Fluorine-induced Suppression of Effective Work Function Lowering in TiN/TiAlC Metal Gate Electrodes

[A-2-06]Flat-Band Voltage Tuning through Al Layer Position Engineering

[A-2-04]Density Functional Theory Analysis of V_t and CMOS Polarity Control in Si High K based FETs