2025 International Conference on Solid State Devices and Materials
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Session Details

Oral Presentation10: Thin Film Electronics: Oxide / Non‐single Crystalline / Novel Process

[N-1]Oxide Semiconductor Devices 1

Tue. Sep 16, 2025 1:30 PM - 3:00 PM JST
Tue. Sep 16, 2025 4:30 AM - 6:00 AM UTC
Room N (416+417, 4th Floor)
Session Chair: Mamoru Furuta (Kochi Univ. of Technology), Jun Koyama (Semiconductor Energy Lab.)
1:30 PM - 2:00 PM JST(4:30 AM - 5:00 AM UTC)

[N-1-01 (Invited)]Oxide semiconductor FET for 3D integration in LSI application

〇Masaharu Kobayashi1 (1. The Univ. of Tokyo (Japan))
2:00 PM - 2:15 PM JST(5:00 AM - 5:15 AM UTC)

[N-1-02]Superlattice ZrO2-Al2O3 Gate Stack of BEOL-Compatible In2O3 FETs with High On/Off Ratio >109 and Synaptic a = -0.63 for 2T0C

〇Zhao-Feng Lou1, Sie Beng Ting2, Yii-Tay Chang1, Che-Chi Cheng1, Shu-Tong Chang3, Ming-Han Liao4, Ling-Yen Yeh5, Shou-Zen Chang5, I-Chun Cheng2, Min-Hung Lee 1,6,7 (1. Program for Semiconductor Devices, Materials, and Hetero-integration, Graduate School of Advanced Technology, National Taiwan Univ. (Taiwan), 2. Graduate Institute of Photonics and Optoelectronics, National Taiwan Univ. (Taiwan), 3. Department of Electrical Engineering, National Chung Hsing Univ. (Taiwan), 4. Department of Mechanical Engineering, National Taiwan Univ. (Taiwan), 5. Powerchip Semiconductor Manufacturing Corp. (Taiwan), 6. Graduate Institute of Electronics Engineering, National Taiwan Univ. (Taiwan), 7. Institute of Applied Mechanics, Nation Taiwan Univ. (Taiwan))
2:15 PM - 2:30 PM JST(5:15 AM - 5:30 AM UTC)

[N-1-03]Electrical Characteristics Improvement and Vth Modification in Ultrathin InOx FETs with AlOx-Interlayer/HfOx Gate Stack

〇Chia-Tsong Chen1, Kasidit Toprasertpong2, Toshifumi Irisawa1, Wen Hsin Chang1, Shinji Migita1, Yukinori Morita1, Hiroyuki Ota1, Tatsuro Maeda1 (1. AIST (Japan), 2. The Univ. of Tokyo (Japan))
2:30 PM - 2:45 PM JST(5:30 AM - 5:45 AM UTC)

[N-1-04]Reduction Parasitic Resistance in Polycrystalline Ga-Doped In2O3 Channel Field-Effect Transistors by Using a Buffer Layer of In2O3-Based Conductive Oxides

〇Hikaru Hoshikawa1, Takanori Takahashi1, Yukiharu Uraoka1 (1. NAIST (Japan))
2:45 PM - 3:00 PM JST(5:45 AM - 6:00 AM UTC)

[N-1-05]Insights into S/D Contact Impacts on Asymmetric Performance of Vertical Channel-All-Around IGZO FETs

〇Xianglie Sun1, Tiantian Wei1, Wei Yu1, Fuwang Yang1, Jiabiao Sun1, Yong Yu1, Shujuan Mao1, Jing Zhang1, Guilei Wang1, Bok-Moon Kang1, Chao Zhao1 (1. Beijing Superstring Academy of Memory Technology (China))
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