2025 International Conference on Solid State Devices and Materials
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Session Details

Short Oral Presentation01: Advanced CMOS: Material Science / Process Engineering / Device Technology

[SO-PS-01]01: Advanced CMOS: Material Science / Process Engineering / Device Technology

Wed. Sep 17, 2025 1:30 PM - 2:00 PM JST
Wed. Sep 17, 2025 4:30 AM - 5:00 AM UTC
Room A (301, 3rd Floor)
Session Chair: Kuniyuki Kakushima (Science Tokyo), Genji Nakamura (Tokyo Electron Ltd.)
1:30 PM - 1:32 PM JST(4:30 AM - 4:32 AM UTC)

[SO-PS-01-01]Influence of Substrate Accepter Concentration on the Density of States in MOS Structures

〇Kaoru Kato1, Hajime Tanaka1, Nobuya Mori1 (1. The Univ. of Osaka (Japan))
1:32 PM - 1:34 PM JST(4:32 AM - 4:34 AM UTC)

[SO-PS-01-02]Impact of a Single Interface-Trapped Charge on Vth Variation in GAA nanosheet FETs Analyzed by 3D TCAD Simulation

〇Takefumi Kamioka1, Junichi Hattori1, Naoya Okada1, Koichi Fukuda1 (1. AIST (Japan))
1:34 PM - 1:36 PM JST(4:34 AM - 4:36 AM UTC)

[SO-PS-01-03]Mean-Free-Path-Based Modeling of Interconnect Resistivity for Cryogenic CMOS

〇Akira Tsuchiya1 (1. The Univ. of Shiga Prefecture (Japan))
1:36 PM - 1:38 PM JST(4:36 AM - 4:38 AM UTC)

[SO-PS-01-04]Threshold Voltage Design for High-Stability and High-Speed Cryogenic SRAM

〇Geng-Lun Li1, Yu-Cheng Lu1, Vita Pi-Ho Hu1 (1. National Taiwan Univ. (Taiwan))
1:38 PM - 1:40 PM JST(4:38 AM - 4:40 AM UTC)

[SO-PS-01-05]A Machine Learning Approach to FEOL/MOL Parasitic Capacitance Extraction for the Complementary FET(CFET)

〇Jaehong Park1,2, Seung Kyu Kim1,2, Johyeon Kim1, Kee-Won Kwon1, Jongwook Jeon1 (1. The Univ. Sungkyunkwan (Korea), 2. Samsung Electronics (Korea))
1:40 PM - 1:42 PM JST(4:40 AM - 4:42 AM UTC)

[SO-PS-01-06]AutoRW-Phys: A Physics-Guided Region-Weighted Model for Fast Parameter Extraction towards SPICE-Compatible RRAM Simulation

〇Zhih-Yun Kuo1, Hao-Siou Huang1, Bo-Cheng Chen1, I-Ling Li1, Ning-Yuan Lue1, Chao-Hui Yeh1 (1. The Univ. of Taiwan (Taiwan))
1:42 PM - 1:44 PM JST(4:42 AM - 4:44 AM UTC)

[SO-PS-01-07]Work Function Engineering in Dual Metal BCAT DRAM for Simultaneous Mitigating GIDL, GIJL, PGE and 1-RD

〇Hwichan - Jeon1, Min-Woo - Kwon1 (1. Seoul National Univ. of Sci. and Tech. (Korea))
1:44 PM - 1:46 PM JST(4:44 AM - 4:46 AM UTC)

[SO-PS-01-08]Dual-Mode Charge Trap Flash Memory Using Nickel-Silicide Schottky-Junction Reconfigurable FETs via Channel Modulation Engineering

〇Ki-Ju Park1, Seong-Hwan Lim1, Jin-Wook Shin2, Jong-Heon Yang2, Won-Ju Cho1 (1. The Univ. of Kwangwoon (Korea), 2. The Lab. of ETRI (Korea))
1:46 PM - 1:48 PM JST(4:46 AM - 4:48 AM UTC)

[SO-PS-01-09]Clarification of the Mechanism of Crystallization
by the Topmost ZrO2 Layer in ZrO2/Hf0.5Zr0.5O2 Stack

〇Rina Takahisa1, Takashi Onaya1,2, Atsushi Tamura1, Koji Kita1 (1. Department of Advanced Materials Science, Graduate School of Frontier Sciences, The Univ. of Tokyo (Japan), 2. Res. Center for Materials Nanoarchitectonics (MANA), National Inst. for Materials Sci. (Japan))
1:48 PM - 1:50 PM JST(4:48 AM - 4:50 AM UTC)

[SO-PS-01-10 (Late News)]Hf/Zr Ratio Adjusting in HfxZr1-xO2 and Conducting Structural Engineering for Capacitor with High Capacitance Density and Low Leakage Current

〇Hong-Yan Zhu1, Yu-Chun Li1, Zi-Ying Huang1, Hao-Lin Liao1, Wei-Min Li2, David Wei Zhang Zhang1, Hong-Liang Lu1 (1. Fudan University (China), 2. Jiangsu Leadmicro Nano Technol Co Ltd (China))
1:50 PM - 1:52 PM JST(4:50 AM - 4:52 AM UTC)

[SO-PS-01-11]A design and comprehensive simulation of a channel-all-around FeFET for high density storage application

〇Xiu Yang1, Hongrui Zhang1, Di Wang1, Kai Xiong1, Xiao Yu1, Bing Chen1, Yan Liu1, Genquan Han1 (1. HangZhou Inst. of Tech., Xidian Univ. (China))
1:52 PM - 1:54 PM JST(4:52 AM - 4:54 AM UTC)

[SO-PS-01-12]La Dipole’s Vfb Roll-Off mechanism and Improved leakage and interface charge performance in dipole Last process

〇Hongmei Zhang1, Yang liu1, YuChun Li1, HaiYang Liu1, Hongliang Liu1, Xiaona Zhu1,2, Shaofeng Yu1, Wei - Zhang1,2 (1. Fudan university (China), 2. Jiashan Fudan Institute (China))
1:54 PM - 1:56 PM JST(4:54 AM - 4:56 AM UTC)

[SO-PS-01-13]Evaluation of Heat-Dissipation Effects in Vertical-Transport Nanosheet FET (VTFET) Considering Various Metal-Contact Configurations

〇Yi-Hsuan Yu1, Pin Su1 (1. National Yang Ming Chiao Tung Univ. (Taiwan))
1:56 PM - 1:58 PM JST(4:56 AM - 4:58 AM UTC)

[SO-PS-01-14]Vertically Stacked Dual-Gate Dynamically Reconfigurable Field Effect Transistor for CMOS-Compatible Adaptive Logic Applications

〇Seung-Hyun Lee1, Won-Ju Cho1 (1. Kwangwoon Univ. (Korea))
1:58 PM - 2:00 PM JST(4:58 AM - 5:00 AM UTC)

[SO-PS-01-15]mm-Wave CMOS Device Optimization and Accurate Noise Deembedding Method Demonstrating Minimum Noise and Super-300GHz fMAX

〇Adhi Cahyo Wijaya1, Jyh Chyurn Guo1 (1. National Yang Ming Chiao Tung University (Taiwan))
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