[17a-K101-1~13] 13.5 デバイス／配線／集積化技術

11:45 〜 12:00英語発表

[17a-K101-11] Design Technology Co-optimization (DTCO) for spacer Design in Gate-All-around Nanosheet FETs

〇(M2)Yaoping Xiao¹, Xiaoran Mei¹, Takuya Saraya¹, Toshiro Hiramoto¹, Masaharu Kobayashi^1,2 (1.IIS, Univ. of Tokyo, 2.d.lab, Univ. of Tokyo)

キーワード：

Design Technology Co-Optimization(DTCO)、Gate-all-around Nanosheet FETs、Power、Performance、area

With continuous feature-size scaling, Gate-all-around Nanosheet (GAANS) has been considered as a candidate for 3nm technology node and beyond because of its excellent gate controllability. However, the trade-off between the lengths of different sections along the channel direction of the device such as gate, spacer and contact in Front-of-Line (FEOL) and Middle-of-Line (MOL) can have a significant impact on the performance . Besides, resistance and capacitance (RC) of Back-End-of-Line (BEOL) interconnects also play significant roles in impacting circuit’s power-performance-area (PPA) . In this work, following the principles of DTCO, we discuss the impact of deveice geometry of a GAA NS FET, as well as RC of interconnects on the power-performance if a ring-oscillator circuit.