講演情報
[17a-K101-12]Comprehensive Study on the Silicon-Nanosheet Thickness Dependence On the Device Performance of Gate-All-Around NFETs
〇(M2)Yaoping Xiao1, Xiaoran Mei1, Takuya Saraya1, Toshiro Hiramoto1, Masaharu Kobayashi1,2 (1.IIS, Univ. of Tokyo, 2.d.lab, Univ. of Tokyo)
キーワード：
Gate all around Nanosheet FETs、k.p model and Boltzmann transport simulations、Sheet thickness
With the continuous scaling of transistors and the reduction in gate length (Lg), short-channel effects (SCE) become increasingly severe. Gate-All-Around Nanosheet (GAA NS) FETs exhibit superior gate control capabilities. It is generally necessary to reduce Lg of devices to scale down Contacted Poly Pitch (CPP) for shrinking standard cell size. At the same time, NS needs to be thinned down to suppress SCE. As NS thickness becomes thin, the quantum confinement(QC) becomes pronounced. In our research. To fully understand the QC and explore the thickness scaling limit, we systematically study the influence of thickness scaling on the performance of GAA NS FETs by using the advanced Multi-Subband Boltzmann Transport Equation(MSBTE) incorporating low-field mobility models and high-field quasi-ballistic transport.