Session Details
[S4]Oxide Semiconductors
Thu. Nov 6, 2025 3:25 PM - 4:55 PM JST
Thu. Nov 6, 2025 6:25 AM - 7:55 AM UTC
Thu. Nov 6, 2025 6:25 AM - 7:55 AM UTC
5F-Meeting Room
Chair:Noboru Ooike(Tokyo Electron), Tomoyuki Suwa(Tohoku University)
[S4-01]Gate-All-Around Vertical InGaZnO Channel Transistor for 4F2 DRAM application
*Keiko Ariyoshi1, Shoichi Kabuyanagi1, Kenichi Haga1, Kei Sakamoto1, Shosuke Fujii1, Takeshi Fujimaki1, Tseng Fu Lu2, Szu Yao Chang2, Chiang-Lin Shih2 (1. KIOXIA Corporation (Japan), 2. Nanya Technology Corporation (Taiwan))
[S4-02]InGeO:F Channel Engineering by Fluorination Based on a GeO2 Buffer Layer with Enhanced Mobility and Negative-Bias Stability
Shundong Hu1,2,3, *Jiayi Wang1,2,3, Kuo Zhang1,2,3, Nannan You1,2,3, Yang Xu1,2,3, Ling Li1,3, Shengkai Wang1,2,3 (1. State Key Laboratory of Fabrication Technologies for Integrated Circuits, Institute of Microelectronics, Chinese Academy of Sciences, Beijing (China), 2. High-Frequency High-Voltage Device and Integrated Circuits R&D Center, Institute of Microelectronics, Chinese Academy of Sciences, Beijing (China), 3. University of Chinese Academy of Sciences (China))
[S4-03]Electrical Characteristics of 3D CMOS Formed with SiGe pFinFET and IGZO nTFT
*Yu-Chao Huang1, Pei-Hsin Wei1, Dun-Bao Ruan2, Kuei-Shu Chang-Liao1 (1. National Tsing Hua University (Taiwan), 2. Fuzhou University (China))
[S4-04]Defect Characterization of 3D Channel-All-Around Transistors Using Variable Photocurrent Method
*Kuo Zhang1,2,3, Jiayi Wang1,3, Shundong Hu1,2,3, Tianhao Liao1,2,3, Huan Liu1,2,3, Yang Xu1,3, Nannan You1,3, Ling Li1,2, Shengkai Wang1,2,3 (1. Key Laboratory of Fabrication Technologies for Integrated Circuits, Chinese Academy of Sciences (China), 2. University of Chinese Academy of Sciences (China), 3. High-Frequency High-Voltage Device and Integrated Circuits R&D Center, Institute of Microelectronics (China))
