Session Details
[P]Poster Session
Tue. Sep 29, 2026 4:00 PM - 6:00 PM JST
Tue. Sep 29, 2026 7:00 AM - 9:00 AM UTC
Tue. Sep 29, 2026 7:00 AM - 9:00 AM UTC
Room A3+A4(3rd floor)
[P-01]Monte Carlo Simulation of the Silicon-Channel Thickness Dependence
of Nanosheet Performance
*Fabian Bufler1, Sylvain Baudot1, Sheng Yang1, Philippe Matagne1, Naoto Horiguchi1, Geert Hellings1 (1. IMEC)
[P-02]Multi-subband Monte Carlo Simulation of Scaled
Forksheet FETs
Luca Donetti1, *Cristina Medina-Bailon1, José Luis Padilla1, Carlos Sampedro1, FRancisco Gamiz1 (1. Nanoelectronics Research Group and CITIC, Univ. of Granada, Granada, Spain)
[P-03]Performance Analysis of Silicon GAA-NS-FETs
*Philippe Blaise1, Daniel Lemus2, Mark Townsend1, Eric Guichard1, Tillmann Kubis2, Josef Weinbub1 (1. Silvaco Inc., 2. Purdue Univ.)
[P-04]Revealing New Leakage Paths in GAAFETs using Predictive First Principle Simulations
*Denis Mamaluy1 (1. Sandia National Labs)
[P-05]Self-Heating and Radiation Hardness Studies of 3nm GAA-FET-Based SRAM with Different Substrate Isolation Techniques
*Albert Lu1, Junipero Verbeke1, Phil Oldiges2, Reza Arghavani2, Hiu Yung Wong1 (1. San Jose State University, 2. Sandia National Laboratories)
[P-06]Circuit-to-Micromagnetics Analysis of Read Disturbance in Two-Terminal SOT-MRAM
*MD NAHID HAQUE SHAZON1, Cheng-Yu Lin1, Azad Naeemi1 (1. Georgia Institute of Technology)
[P-07]Insights into the Retention Behavior of Filamentary OxRAM Cells using Calibrated kMC Method
*Ilia Kolevatov1, Gueorgui Nikiforov1, Steven Soss1, Georg Wolf1, Hsin-Yu Chen1, Robert Seidel1, Dirk Fuhrmann1, Alban Zaka1 (1. Globalfoundries)
[P-08]TCAD-Based Word Line Driver Optimization for NAND-type 3D Flash Memory Scaling
*Sudarshan Narayanan1, Qinghua Zhao1, Satoru Mayuzumi1, Derek Dou1, Chao Qin1, Mohan Dunga1 (1. Sandisk Technologies Inc.)
[P-09]Avalanche Breakdown in IGBT Corners with VLD Termination: Quantitative 3D TCAD Investigation
*Massimiliano Galvagno1, Simone Dario Mariani2, Paola Zuliani2, Salvatore-Fabio Liotta3, Silvia Cannizzaro3, Gerardo Malavena1, Christian Monzio Compagnoni1, Alessandro Sottocornola Spinelli1 (1. Politecnico di Milano, piazza L. da Vinci 32, 20133 Milano, Italy, 2. STMicroelectronics, via C. Olivetti 2, 20864 Agrate Brianza, Italy, 3. STMicroelectronics, strad. Primosole 50, 95121 Catania, Italy)
[P-10]Physics-Informed Compact Modeling of Leakage and Breakdown in GaN-on-Si Devices
*Ilya Rumyantsev1, Jeff Steinfeldt2, Nyles Cody1, Shuyi Li1, Daniel Connelly1, Marek Hytha1, Robert J Mears1, Daniel Bailey3, Jonathan W Anderson3, Edwin Piner3 (1. Atomera Inc., 2. Sandia National Lab., 3. Texas State Univ.)
[P-11]SOI PeDMOS RON-BV-IOFF tradeoff optimization through TCAD simulations
*Joris Lacord1, Ayoub Boutayeb2, Dominique Golanski2, Sylvain Joblot2, Fabienne Ponthenier1 (1. CEA-Leti, 2. STMicroelectronics)
[P-12]Double-Gate LDMOS Transistors with Exceptional Figure-of-Merit Exceeding 700 kW/mm²
Elham Mashhadi1, *William Gerard Vandenberghe2, Sara Ghazvini2, Ali Saadat3, Hal Edwards4, Sujatha Sampath4, Daniel Pham4 (1. Department of Electrical and Computer Engineering, The University of Texas at Dallas, Richardson, TX 75080, USA, 2. Department of Material Science and Engineering, The University of Texas at Dallas, Richardson, TX 75080,USA, 3. Department of Kilby Labs, Texas Instruments Inc., Richardson, TX 75080, USA, 4. Department of Analog Technology Development, Texas Instruments Inc., Richardson, TX 75080, USA)
[P-13]Unified TCAD Simulation Framework for InGaAs/InP Single-Photon Avalanche Diodes
*M. Saqlain Khan1, Andreas Woerl1, Frank Rutz1 (1. Fraunhofer-Institute for Applied Solid State Physics IAF)
[P-14]Revisiting Random Dopant Fluctuation at Cryogenic
Temperature: the Effect of Incomplete Ionization
*Huawei Tang1, Yu Wu1, Junjie Hao1, Shaofeng Yu1 (1. Fudan Univ.)
[P-15]Hot Carriers and Self-Heating Effects in FD-SOI Devices at Cryogenic Temperatures
Bhargav Nallan Chakravartula1, Ziyi Wang2, Siddhant Gangwal1, Katerina Raleva3, *Dragica Vasileska1, Michael Povolotskyi4 (1. Arizona State University, 2. onsemi, 3. University Ss Cyril and Methodius, 4. Amentum Solutions)
[P-16]DFT Modeling of O2-Driven Fragmentation and Islanding from MoS2 Nanoworms
Suman Gora1, Jay Singh1, *Medha Shukla1, Arnab Datta1 (1. Indian Institute of Technology (IIT) Roorkee)
[P-17]Modeling and Simulation of Exciton Dynamics in Transition Metal
Dichalcogenides Heterostructures
*Rohit Ramesh Nimje1, Athira S1, Vignesh S1, Ashutosh Mahajan1 (1. Centre for Nanotechnology Research, Vellore Institute of Technology, Vellore-632014, India.)
[P-18]Analytical SOT MRAM Modeling : From Deterministic to Fokker-Planck based Stochastic Switching
*Trisha Bhowmik1,2, Maxwel Gama Monteiro1, Siddharth Rao1, Yang Xiang1, Jan Van Houdt1,2, Kristiaan Temst1,2, Fernando Garcia Redondo1, Gouri Sankar Kar1 (1. Indus., 2. Univ.)
[P-19]Quasi-Bound State Tunneling in GaN Devices using 2D NEGF with Supercell Mode-Space Method
*Heonseok Oh1, Phil-Hun Ahn1, Jooseok Kim1, Mincheol Shin1 (1. Korea Advanced Inst. of Sci. and Tech.)
[P-20]Semi-Classical Monte Carlo Simulation of Contact Geometry Effect on Source/Drain Junction Resistance in N-Type Si Fin and Nanosheet FETs
*Uiho Lee1, Jaeyeon Kim1, Jiwon Chang1 (1. Yonsei Univ.)
[P-21]Carrier Density Dependent Transport in Monolayer WS2
*Nils Vansteenvoort1,2, Andrés Hidalgo2, Gautam Gaddemane2, Bart Sorée1,2, Maarten L Van de Put2 (1. Univ. KU Leuven, 2. Inst. Imec)
[P-22]Lattice-Based Quantum Phonon Transport in FD-SOI Transistors
*David Mai1, Dirk Schulz1 (1. TU Dortmund University)
[P-23]FE-NEGF for Cryogenic Thermal Management
*Arnaud Lorin1, Jing Li1 (1. Univ. Grenoble Alpes, CEA, Leti)
[P-24]A Fokker-Planck Approach for Modeling Temperature-Dependent Two-Phase Switching Dynamics in Ferroelectrics
*Wei Zhang1, Leming Jiao1, Jianze Wang1, Xiao Gong1, Xuanyao Fong1 (1. National Univ. of Singapore)
[P-25]Multi-Stage Etch Recipe Inverse Design: Bridging Expert Behavioral Cloning and Reinforcement Learning
*Jianming Guo1, Mingqiang Geng1, Zhengming Liu2, Dianyu Qi1, Dong Ni1, Dawei Gao1,2 (1. Zhejiang Univ., 2. Zhejiang ICsprout Semiconductor Co., Ltd.)
[P-26]Layer-by-layer oxidation of HfSe2 and formation of clean van der Waals interfaces with 2D semiconductors: A first-principles molecular dynamics study
*Joonho Park1, Yong-Hoon Kim1 (1. Korea Advanced Institute of Sci. and Tech.)
[P-27]Twisting in High Aspect Ratio Etching with Charging Effects as a Stochastic Mechanism
*Taishi Ikeda1, Hisashi Kotakemori1, Satoshi Nakamura1, Kenta Yashima1, Takumi Ohmura1, Yasuyuki Kayama1, YunTae Lee2, Yukihide Tsuji2, Shinwook Yi2, Moon-Hyun Cha2, Jaehoon Jeong2 (1. Samsung Japan Corp., 2. Samsung Electronics Corp.)
[P-28]Impact of Surface Charging on Feature Profile Evolution in 3D NAND Pillar Etching
*Siddharth Mohanty1, Vatsal Thakor2, Om Maheshwari1, Nihar Ranjan Mohapatra1 (1. Indian Inst. of Tech. Gandhinagar, India, 2. Nirma Univ., India)
[P-29]Pulsed Bias Etching of Silicon Pillar Arrays: Experiment and Surface-Memory Simulation of Loading Control
*Jianming Guo1, Zhengming Liu2, Mingqiang Geng1, Kunrun Song2, Huiyun Jiang1,2, Dong Ni1, Dawei Gao1,2 (1. Zhejiang Univ., 2. Zhejiang ICsprout Semiconductor Co., Ltd.)
[P-30]Experiment-Based Modeling of Wafer-to-Wafer Bonding for 3D Integration
*Hyuga Ishii1, Takashi Shimura2, Ryota Ogata1, Hayato Kitagawa1, Taisuke Yamamoto1, Fumihiro Inoue1 (1. YOKOHAMA National University, 2. ESTECH Corp.)
[P-31]OPC+: GPU-Accelerated Lithography Simulation with Contour-Based Calibration and Unified Inverse Mask Optimization
*Po-Hsun Fang1, Pokai Chang1, Kuan-Hsun Wang1, Zhi-Sheng Wang1, Han-Xuan Huang1, Shie-Yuan Wang1, Peichen Yu1 (1. National Yang Ming Chiao Tung Univ.)
[P-32]Multi-Phase-Field Modeling of Thin-Film Silicidation
Christophe Pixius1, *Ferdinand Schulz1, Sanjukta Chowdhury1, Eberhard Baer1, Christopher Straub1, Andreas Rosskopf1 (1. Fraunhofer IISB)
[P-33]SEMulator3D® Linking Deposition Process to Electrical Metrics-Accelerated WAT Learning
*Xing Qin1, Tristan Yang1, Deyong Kong1, Xiaoqiang Wan1 (1. Lam Research Corp.)
[P-34]SPER-Driven Dislocation Nucleation and Uphill
Diffusion Modeling for Advanced Semiconductor
Processing
*Chihak Ahn1, Alexander Schmidt2, Joohyun Jeon2, Seungmin Lee2, Woosung Choi1, Jaehoon Jeong2 (1. Samsung Semiconductor Inc., 2. Samsung Electronics)
[P-35]Feature Charging During Cryogenic Plasma Etching
Yeon Geun Yook1, Chenyao Huang1, Yifan Gui1, *Mark J. Kushner1 (1. Univ. of Michigan)
[P-36]A Covariance Matrix Adaptation Evolutionary Strategy Parameter Extractor for BSIM-CMG
*Jen-Hao Chen1, Ahtisham Pampori1, Chenming Hu1, Sayeef Salahuddin1 (1. Univ. of California, Berkeley)
[P-37]An Accurate Temperature-Dependent Compact Model for Ferroelectric Capacitors
*Nandakishor Yadav1, Phuoc Khang Nguyen1, Maximilian Lederer1, Jacob Syndikus1, Tianren Zhang1, David Lehninger1, Konrad Seidel1, Thomas Kaempfe1 (1. Fraunhofer Institute for Photonic Microsystems IPMS Dresden)
[P-38]Comprehensive SPICE Compact Modeling of Split-Gate Embedded Flash Memory for Transient and Worst-Case Operation Failure Simulation
*Dongwoo Lim1,2, Kiyoung Kim2, Hyungcheol Shin1 (1. Seoul National Univ., 2. Samsung Electronics Co., Ltd.)
[P-39]SPICE Modeling Method of Reverse Recovery Based on TCAD Analysis
*Emiru Baba1, Shigeru Nakajima1, Tsuyoshi Kachi1, Takuma Hara1, Kozo Kinoshita1 (1. Toshiba Electronic Devices & Storage Corporation)
[P-40]First-principles calculation of free carrier absorption in 4H-SiC
*Masahiko Matsubara1, Enrico Bellotti1 (1. Boston University)
[P-41]Low-temperature enhancement of quantum hybridization-induced negative differential resistance in a Pb-free 1D halide perovskite
*Jeongwon Lee1, Tae Hyung Kim1, Juho Lee1, Yong-Hoon Kim1 (1. Korea Advanced Inst. of Sci. and Tech.)
[P-42]Multi-space density functional simulations of WSe2 p-n junctions
*Hyeonjun Kang1, Taehyung Kim1, Juho Lee1, Ryonggyu Lee1, Yonghoon Kim1 (1. Korea Advanced Inst. of Sci. and Tech. (KAIST))
[P-43]Machine Learning Framework for the Inverse Design of Tight-Binding Parameters in Compound Semiconductors
*Kaito Seike1, Shingo Sato1 (1. Kansai University)
[P-44]A Machine-Learning Accelerated Atom-to-Transistor Simulation Framework
Pratik Brahma1, *Krishna Bhattaram1, Sayeef Salahuddin1 (1. University of California, Berkeley)
[P-45]Physics-Enhanced LSTM Modeling of Electric Double-Layer Transistors
Haoran Yang1,2, *Shuaidi Zhang1,2, Yue Zhao1,2, Ling Li1,2 (1. Inst. of Microelectronics, CAS, 2. Univ. of CAS)
[P-46]Power–Performance Assessment of 48 nm Gate-Pitch CFETs Using Experimentally Calibrated Physics-Informed ANN Models
*Yu-Wen Xu1, Yiming Li1, Min-Hui Chuang1, Yun Tai1 (1. National Yang Ming Chiao Tung Univ.)
[P-47]AI-driven TCAD Surrogate Modeling and Multi-Objective Optimization for Accelerated Technology Development
*Derek Dou1, Sudarshan Narayanan1, Qinghua Zhao1, Chao Qin1, Mohan Dunga1 (1. Sandisk Tech., Inc.)
[P-48]Accelerating Simulation of General Gate-All-Around Transistors via a Quasi-1D Model
*Gyubeen Kim1, Kwang-Woon Lee2, Sung-Min Hong2 (1. Department of Semiconductor Eng., Gwangju Inst. of Sci. and Tech., 2. Department of Electrical Eng. and Computer Sci., Gwangju Inst. of Sci. and Tech.)