Session Details
[Tu-P]Power Devices
Tue. Sep 29, 2026 4:00 PM - 6:00 PM JST
Tue. Sep 29, 2026 7:00 AM - 9:00 AM UTC
Tue. Sep 29, 2026 7:00 AM - 9:00 AM UTC
Poster-B(4th Floor, G401+G402)
[Tu-P-49]Impact of Substrate Dislocations on the Leakage Characteristics of 650V SiC Power MOSFETs
*Fabiana Vento1, Giovanni Maira1, Andrea Russo1, Nicolo Piluso1, Enzo Fontana1, Cristiano Calabretta1, Nicoletta Spampinato1, Alice Lombardo1, Damiana Spagnuolo1, Giuseppe Arena1, Andrea Severino1 (1. Indus. STMicroelectronics (Italy))
[Tu-P-50]Impact of micro-pits defects on the low temperature electrical characteristics of 650 V 4H-SiC power MOSFETs
Marco Zignale1, *Patrick Fiorenza1, Salvatore Ethan Panasci1, Alberto Catena2, Francesco Maria Fiorino2, Filippo Giannazzo1, Fabrizio Roccaforte1 (1. CNR-IMM (Italy), 2. STMicroelectronics (Italy))
[Tu-P-51]Mitigation of process-induced variations in highly-scaled trench MOSFETs
Rajni K Sah1, *Dallas T Morisette1, James A Cooper1 (1. Purdue University (USA))
[Tu-P-52]Impact of Double-Epitaxial Drift Layer on JFET-Width-Dependent Characteristics in 1.2-kV 4H-SiC MOSFETs
*Junki Jung1, Sumin Park1, Seungri Yang1, Hyun Park2, Sangik Cheon2, Yehwan Kang2, Jaejin Song3, Derek D. Lee3,Ogyun Seok1 (1. Pusan National University (Korea), 2. SK Powertech (Korea), 3. SK Keyfoundry (Korea))
[Tu-P-53]Non-Monotonic Reverse Recovery Behavior in 1.2 kV SBD-Embedded SiC MOSFETs with Different SBD-P-well Ratios
*Wonyoung Shin1, Gyuhyeok Kang1, Jeongtae Kim1, Jinwoo Park1, Juhui Kim1, Sihyun Kwon1, Hyojoon Seo2, Soontak Kwon2, Ogyun Seok1 (1. Pusan National University (Korea), 2. TRinno Technology Co., Ltd (Korea))
[Tu-P-54]Design optimization for switching performance characteristics in 1.2kV SiC trench MOSFET
*Juyun Ha1, Kwangwon Lee1, Taeseop Lee1, Seunghyun Hong1, Bongyong Lee1 (1. onsemi (Korea))
[Tu-P-55]Short-Circuit and Surge-Current Robustness Limit of SiC MOSFETs at Negative and Elevated Temperatures
*Mohamed Alaluss1, Dominik-Tommi Suszek1, Madhu Lakshman Mysore1, Maximilian Goller1, Josef Lutz1, Thomas Basler1 (1. Chemnitz Univ. of Tech. (Germany))
[Tu-P-56]Investigation of Drain-Induced Threshold Voltage Shifts in 1200V SiC MOSFETs
*Woongsun Kim1, Naeem Islam1, Shane Stein1, Sei-Hyung Ryu1, Adam Barkley1, Elif Balkas1 (1. Wolfspeed Inc. (USA))
[Tu-P-57]Enhanced High-Temperature Body Diode Stability and Low Switching Losses in 1.2 kV 4H-SiC Planar MOSFETs via Optimized Current Spreading Layer (CSL)
*Yeongeun Park1, Sangik Cheon2, Kyungeun Park2, In-Hwan Ji1, Derek D Lee1 (1. SK Keyfoundry (Korea), 2. SK Powetech (Korea))
[Tu-P-58]Cell Pitch Optimization for Ron,sp < 2 mΩ-cm2 for 1200V Planar SiC MOSFETs
Aditi Agarwal1, *Rahul Potera1, Bohee Kang1, David Sheridan1 (1. Alpha and Omega Semiconductors (USA))
[Tu-P-59]Investigation of the Short-Circuit Failure Mechanisms in 1700 V 4H-SiC VDMOSFETs
Yu-Jen Chen1, *Shih-Chiang Shen1, Chih-Ming Tzeng1, Chih-Ming Lai1, Tao-Chih Chang1 (1. Indus. Tech. Res. Inst. (Taiwan))
[Tu-P-60]Comprehensive Experimental Analysis on SmartSiCTM On-state Benefits for 1700V Power Components from Room to High temperature
Francesco Serra di Santa Maria1, Cyrille Le Royer1, Jérôme Biscarrat1, Romain Lavieville1, Walter Gonçalez Filho1, Walter Schwarzenbach2, Frédéric Allibert2, *Philippe Godignon1 (1. CEA-Leti (France), 2. Soitec (France))
[Tu-P-61]Design Study of Asymmetric Pillar for Robustness Enhancement in 4H-SiC Semi-Superjunction Geometry
*Yuzuki Hayakawa1, Daisuke Iizasa1, Seigo Mori1, Yuki Nakano1 (1. ROHM Co., Ltd. (Japan))
[Tu-P-88LN]Experimental Demonstration of a Self-Aligned Shielding-Gate 1.2 kV 4H-SiC VDMOSFET with Low Reverse Transfer Capacitance
*Fu-Chen Liang1, Wei-Jhe Liao1, Han-Wei Chen1, Li-Jung Lin2, Chun-Hao Lai2, Shih-Lung Tsai3, Chien-Chih Lu3, Bing-Yue Tsui1 (1. National Yang Ming Chiao Tung University (Taiwan), 2. Mi Semiconductor Co., Ltd. (Taiwan), 3. Mosel Vitelic Inc. (Taiwan))