Session Details

[A-3]Process Technology and Characterization

Wed. Sep 17, 2025 9:00 AM - 10:30 AM JST
Wed. Sep 17, 2025 12:00 AM - 1:30 AM UTC
Room A (301, 3rd Floor)
Session Chair: Genji Nakamura (Tokyo Electron Ltd.), Kasidit Toprasertpong (The Univ. of Tokyo)

[A-3-01]Interface trap density evaluation of off-angle Si(110)/SiO2 interface:Toward understanding of interface properties in advanced MOSFET

〇Ryotaro Shimura1, Eishin Nako1, Koji Matsumoto2, Akihiro Suzuki2, Hiroaki Yamamoto2, kazuhito Matsukawa2, Mitsuru Takenaka1, Shinichi Takagi1, Kasidit Toprasertpong1 (1. The Univ. of Tokyo (Japan), 2. SUMCO Corp. (Japan))

[A-3-02]Unveiling Ferroelectric Properties of Co-Injected ALD HfxZr1-xO2: A Study of Thickness, Composition, and Cryogenic Behavior (73 to 300 K)

〇Kyungsoo Park1, Minhyuk Kim1, Chulwon Chung1, Sunbum Kim1, Sangkuk Han1, Changhwan Choi1,2 (1. Division of Materials Science and Engineering, Univ. of Hanyang (Korea), 2. Department of Semiconductor Engineering, Univ. of Hanyang (Korea))

[A-3-03]Ti-Based Spacer Approach for Semi-Damascene Spacer-is-Dielectric SADP Process Integration at MP18 Demonstration

〇Vincent Renaud1, Gilles Delie1, Debanjan Jana2, Yiting Sun2, Miguel De Abreu Neto3, Sungdae Woo4, David De Roest2, Hyungjoo Shin4, Andrey Sokolov4, Daniele Piumi2, Laurent Souriau1, Chen Wu1, Seongho Park1, Zsolt Tokei1 (1. Imec (Belgium), 2. ASM Belgium (Belgium), 3. ASM Japan (Japan), 4. ASM Korea (Korea))

[A-3-04]Effective Deep Learning Technology for Predicting High-Aspect Ratio Contact Hole Striation Problem in 3D V-NAND Flash Memory

〇BYUNG YONG CHOI1, HOYUN JUNG1, JONGIK HONG1, YOUNGCHAN PARK1, BONG-TAE PARK1, SEUNGWAN HONG1, SUNG HOI HUR1 (1. Samsung Electronics Co., Ltd. (Korea))

[A-3-05]Accurate Si3N4 Wet Etching Rate Prediction with Small Training Data by Gaussian Process Regression

〇Yusuke Hirata1, Koki Shibata1, Naoko Misawa1, Takashi Ota3, Yuki Yoshinaga3, Chihiro Matsui1, Ken Takeuchi1,2 (1. Department of Electrical Eng. and Info. Systems, The Univ. of Tokyo (Japan), 2. Systems Design Lab., Graduate School of Eng., The Univ. of Tokyo (Japan), 3. Cleaning Equipment Development Operations, SCREEN Semiconductor Solutions Co., Ltd. (Japan))

[A-3-06]”Characterization of Plasma-induced Damage on TiN/HfO2/SiO2 Stacked Structure during Multi-Vt Process Using Different Gas Chemistries”

〇Hidefumi HIRABAYASHI Hirabayashi1, Satoshi Sakai1, Kiyohiko Sato1, Naoyuki Kofuji1, Makoto Miura1 (1. Hitachi High-tech Corporation (Japan))