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Advanced FET Technologies & OptoelectronicsThin film process

[S3]Advanced FET Technologies & Optoelectronics

Thu. Nov 6, 2025 1:00 PM - 3:10 PM JST
Thu. Nov 6, 2025 4:00 AM - 6:10 AM UTC
5F-Meeting Room
Chair:Noriyuki Taoka(Aichi Institute of Techology), Mitsuru Sometani(National Institute of Advanced Industrial Science and Technology (AIST))
1:00 PM - 1:30 PM JST(4:00 AM - 4:30 AM UTC)

[S3-01]Area Selective Deposition of Dielectric Film by Surface Passivation for Bottom-Up Nanopatterning Fabrication

*Shinichi Ike1, Yumiko Kawano1, Genki Hayashi1, Shuji Azumo1, Yusaku Kashiwagi1, Tetsuya Goto1 (1. Tokyo Electron Technology Solutions Limited (Japan))
Comment()
1:30 PM - 1:50 PM JST(4:30 AM - 4:50 AM UTC)

[S3-02]Sub 0.5 nm-EOT and Low Leakage Current Density in p-Ge MOS Capacitors Achieved by Interface Engineering

*Huan Wu1, Kuei-Shu Chang-Liao1,2 (1. College of Semiconductor Research, National Tsing Hua University (Taiwan), 2. Department of Engineering and System Science, National Tsing Hua University (Taiwan))
Comment()
1:50 PM - 2:10 PM JST(4:50 AM - 5:10 AM UTC)

[S3-03]Low Temperature PMA Effect on SiO2/GeO2 Gate Stack
for Improvement of Electrical Characteristics and its VFB Controllability

*Hajime Kuwazuru1, Dong Wang2, Keisuke Yamamoto2,3 (1. IGSES, Kyushu Univ. (Japan), 2. FES, Kyushu Univ. (Japan), 3. REISI, Kumamoto Univ. (Japan))
Comment()
2:10 PM - 2:30 PM JST(5:10 AM - 5:30 AM UTC)

[S3-04]Roughness Resistance of Si(551) Surface under Wet Cleaning Evaluation toward Next-Generation CMOS Technologies

*Nawaphorn Kuhakongkiat1, Shungo Nagata1, Akihiro Suzuki2, Hiroaki Yamamoto2, Kazuhito Matsukawa2, Koji Matsumoto2, Ryo Yokogawa1, Akinobu Teramoto1 (1. Hiroshima University (Japan), 2. SUMCO (Japan))
Comment()
2:30 PM - 2:50 PM JST(5:30 AM - 5:50 AM UTC)

[S3-05]Fabrication and evaluation of GeSn photodiodes with metal-interlayer-semiconductor-metal structure formed at an ultra-low temperature (200 ℃)

*Yajun Feng1, Genya Kuroeda1, Keisuke Yamamoto2,3, Shigehisa Shibayama4, Osamu Nakatsuka4,5, Dong Wang1,3 (1. IGSES, Kyushu Univ. (Japan), 2. RESI, Kumamoto Univ. (Japan), 3. FES, Kyushu Univ. (Japan), 4. GSE, Nagoya Univ. (Japan), 5. IMaSS, Nagoya Univ. (Japan))
Comment()
2:50 PM - 3:10 PM JST(5:50 AM - 6:10 AM UTC)

[S3-06]Reverse current suppression via mesa depth control in GeSn-based p-n junction diodes

*Kei Yamamoto1, Shigehisa Shibayama1, Mitsuo Sakashita1, Masashi Kurosawa1, Osamu Nakatsuka1,2 (1. Graduate School of Engineering, Nagoya Univ. (Japan), 2. IMaSS, Nagoya Univ. (Japan))
Comment()
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