[OP-01]Welcome Address
◯T. Kanayama1(1.AIST(Japan))
2016 International Conference on Solid State Devices and Materials
2016年9月26日〜9月29日Tsukuba International Congress Center, Tsukuba, Japan
当該イベント内で検索します。
検索する
2016 International Conference on Solid State Devices and Materials
2016年9月26日〜9月29日Tsukuba International Congress Center, Tsukuba, Japan
当該イベント内で検索します。
検索する検索結果(734)
[OP-02]Welcome Address
◯N. Yokoyama1(1.JSAP(Japan))
[OP-03]SSDM Award/ SSDM Paper Award Ceremony
[PL-1-01]Future of Television: 8K Super Hi-Vision
◯T. Saito1(1.NHK Science & Technology Research Laboratories (Japan))
[PL-2-01]Crossbar Arrays for Storage Class Memory and Non-von Neumann Computing
◯G. W. Burr1(1.IBM Almaden Research Center(United States of America))
[PL-2-02]Step Back for Going Beyond
◯A. Toriumi1(1.Univ. of Tokyo(Japan))
[A-1-01(Invited)]Monolithic 3D (M3D) Complementary Metal-Oxide-Semiconductor (CMOS)-Nano-Electromechanical (NEM) Hybrid Circuits for Low-Power and High-Speed Reconfigurable Logic (RL) Applications
○W. Y. Choi1(1.Sogang Univ.(Korea))
[A-1-02(Invited)]Stackable MoS2 FinFETs Using Solid CVD Developed Through Fully CMOS-Compatible Process Technology
○M. Chen1, K. Li1, L. Li2, M. Li2,3, Y. Chang4, C. Lin1, Y. Chen1, C. Chen1, B. Wu1, C. Wu1, Y. Lee1, J. Shieh1, W. Yeh1, P. Su5, T. Wang5, F. Yang3, C. Hu6(1.National Nano Device Labs.(Taiwan), 2.King Abdullah Univ. of Sci. and Technology(Saudi Arabia), 3.Academia Sinica(Taiwan), 4.NCTU(Taiwan), 5.Dept. of Electronics Eng., NCTU(Taiwan), 6.Univ. of California, Berkeley(USA))
[A-1-03]A New Scale-Length Model for Short-Channel Monolayer and Bilayer Transition Metal Dichalcogenide (TMD) Field-Effect Transistors
○W. You1, P. Su1(1.NCTU(Taiwan))
[A-1-04]Impacts of Device Design and Variability on 6T/8T SRAM Cells with MoS2-n/WSe2-p MOSFETs for 5.9nm node
○C. Yu1, P. Su1, C. Chuang1(1.NCTU(Taiwan))
[A-2-01(Invited)]Experimental Demonstration of Negative Capacitance epi-Ge/Si FETs with Ferroelectric Hf-based Oxide Gate Stack for Swing Sub-60mV/dec and Hysteresis-Free
○M. H. Lee1, P. G. Chen1,2, C. Liu3, K. T. Chen4, M. J. Xie1, S. N. Liu1, H. H. Chen1, C. H. Tang1, J. W. Lee1, W. H. Tu2, K. S. Li5, M. C. Chen5, M. H. Liao2, C. Y. Chang3,6, C. H. Cheng1, S. T. Chang4, C. W. Liu2(1.National Taiwan Normal Univ.(Taiwan), 2.National Taiwan Univ.(Taiwan), 3.NCTU(Taiwan), 4.National Chung Hsing Univ.(Taiwan), 5.National Nano Device Lab.(Taiwan), 6.Academia Sinica(Taiwan))
[A-2-02]Advantages of Silicon-on-Insulator FETs over FinFETs in Steep Subthreshold Swing Operation in Ferroelectric Gate FETs
○H. Ota1, S. Migita1, J. Hattori1, K. Fukuda1, A. Toriumi2(1.AIST(Japan), 2.Univ. of Tokyo(Japan))
[A-2-03]New Findings on the Gate-Length Dependence of Subthreshold Swing for Ultra-Thin-Body Negative Capacitance FETs
○C. P. Tsai1, P. Su1(1.NCTU(Taiwan))
[A-2-04]Effects of Impurity and Composition Profile Steepness on Electrical Characteristics of GaAsSb/InGaAs Hetero-junction Vertical TFETs
○T. Gotow1,3, M. Mitsuhara2,3, T. Hoshi2,3, H. Sugiyama2,3, M. Takenaka1,3, S. Takagi1,3(1.Univ. of Tokyo(Japan), 2.NTT Device Tech. Labs.(Japan), 3.JST-CREST(Japan))
[A-2-05]InGaAs/Si Heterojunction Tunnel FET with Modulation-doped Channel
○K. Tomioka1,2, F. Ishizaka1, J. Motohisa1, T. Fukui1(1.Hokkaido Univ.(Japan), 2.JST-PRESTO(Japan))
[A-3-01]Evaluation of Effective Mass of Inversion-layer Holes in Strained-Si pMOSFETs utilizing Shubnikov de-Haas (SdH) Oscillation
A. Shimada1, R. Nakane1, M. Takenaka1,2,○S. Takagi1,2(1.Univ. of Tokyo(Japan), 2.JST-CREST(Japan))
[A-3-02(Invited)]Carrier Transport Analysis of High-performance Poly-Si Nanowire Transistors
○M. Oda1, K. Sakuma1, Y. Kamimuta1, M. Saitoh1(1.Toshiba Corp.(Japan))
[A-3-03]On the Drain Bias Dependence of Tunnel FETs
○K. Fukuda1, T. Mori1, H. Asai1, J. Hattori1, W. Mizubayashi1, Y. Morita1, H. Fuketa1, S. Migita1, H. Ota1, M. Masahara1, K. Endo1, T. Matsukawa1(1.AIST(Japan))
[A-4-01(Invited)]InGaAs-on-Si(Ge) 3D Monolithic Integration for CMOS and More-than-Moore Technologies
○V. V. Deshpande1, V. Djara1, T. Morf1, P. Hashemi2, E. O'Connor1, K. Balakrishnan2, D. Caimi1, M. Sousa1, J. Fompeyrine1, L. Czornomaz1(1.IBM Research GmbH(Switzerland), 2.IBM T.J. Watson Research Center(USA))
[A-4-02]Reliability Analysis for Monolithic 3D UTB GeOI and SOI 6T SRAM Cells considering Interlayer Coupling
○V. P. -H. Hu1(1.National Central Univ.(Taiwan))
[A-4-03]A New NBTI Lifetime Prediction Method for Deeply Scaled pMOSFETs
C. Zhang1, Y. Liao1, Y. Xu2,○X. Ji1(1.Nanjing Univ.(China), 2.Nanjing Univ. of Posts and Telecommunications(China))
[A-5-01(Invited)]Enabling Hetero-integration of III-V and Ge-based Transistors on Silicon with Ultra-thin Buffers formed by Interfacial Misfit Technique
○X. Gong1, S. Yadav1, K. Goh1, K. Tan2, A. Kumar1, K. Low1, B. Jia2, S. Yoon2, G. Liang1, Y. Yeo1(1.National Univ. of Singapore(Singapore), 2.Nanyang Technological Univ.(Singapore))
[A-5-02]Theoretical Investigation and Benchmarking of Intrinsic Drain-Induced-Barrier-Lowering (DIBL) for Ultra-Thin-Body III-V-on-Insulator n-MOSFETs
○C. -L. Yu1, C. -H. Yu1, P. Su1(1.NCTU(Taiwan))
[A-5-03]An Investigation of the Parasitic RC Effects in Nano-scaled FinFETs and Its Impact on SRAM Cells
○B. R. Huang1, F. H. Meng1, Y. C. King1, C. J. Lin1(1.National Tsing Hua Univ.(Taiwan))
[A-5-04]On the Characterization of Hot Carrier Effect in Fully Depleted SOI and GeOI MOSFETs under Circuit-Speed Random Stress
○R. Cheng1, W. Chen1, D. -W. Wang1, J. Lu2, R. Zhang1, W. -Y. Yin1, Y. Zhao1(1.Zhejiang Univ.(China), 2.Hunan Univ.(China))
[A-6-01(Invited)]Bias Temperature Instability in Tunnel FETs
○W. Mizubayashi1, T. Mori1, K. Fukuda1, Y. Ishikawa1, Y. Morita1, S. Migita1, H. Ota1, Y. X. Liu1, S. O'uchi1, J. Tsukada1, H. Yamauchi1, T. Matsukawa1, M. Masahara1, K. Endo1(1.AIST(Japan))
[A-6-02]Performance Improvement in Uniaxially Tensile Stressed GeSn FinTFET Investigated by Simulation: Impact of Stress Direction
○H. Wang1, G. Han1, Y. Liu1, C. Zhang1, J. Zhang1, Y. Hao1(1.Xidian Univ.(China))
[A-6-03]Tunnel FinFET CMOS Inverter with Very Low Short-Circuit Current for Ultra-Low Power IoT Application
○Y. Morita1, K. Fukuda1, Y. Liu1, T. Mori1, W. Mizubayashi1, S. O'uchi1, H. Fuketa1, S. Otsuka1, S. Migita1, M. Masahara1, K. Endo1, H. Ota1, T. Matsukawa1(1.AIST(Japan))
[A-7-01]On the Variability of Tunnel Field-Effect Transistors: Suppression of BTBT Fluctuation by Tunneling Probability Enhancement
○T. Mori1, S. Migita1, K. Fukuda1, H. Asai1, Y. Morita1, W. Mizubayashi1, Y. Liu1, S. O'uchi1, H. Fuketa1, S. Otsuka1, T. Yasuda1, M. Masahara1, H. Ota1, T. Matsukawa1(1.AIST(Japan))
[A-7-02]Drain-Bias Dependency on Statistical Variability for Tunnel Field-Effect Transistors
○W. Y. Choi1, S. H. Choi1, J. W. Lee1, I. Huh1(1.Sogang Univ.(Korea))
[A-7-03(Late News)]A Study on the Correlation between SRAM Power-up State and Transistor Variation
○K. Takeuchi1, T. Mizutani1, T. Saraya1, H. Shinohara2, M. Kobayashi1, T. Hiramoto1(1.Univ. of Tokyo(Japan), 2.Waseda Univ.(Japan))
[A-7-04(Late News)]Parallel Programmable Non-volatile Memory Using Normal SRAM Cells
○T. Mizutani1, K. Takeuchi1, T. Saraya1, H. Shinohara2, M. Kobayashi1, T. Hiramoto1(1.Univ. of Tokyo(Japan), 2.Waseda Univ.(Japan))
[A-7-05(Late News)]The Experimental Observation of Soft-Error Enhanced NBTI Degradation in Trigate FinFETs for the near-Cosmic Exploration of Drones
E. Hsieh1, C. Wu1,○S. Chung1, R. Huang2, C. Tsai2, T. Yew2(1.NCTU(Taiwan), 2.UMC(Taiwan))
[A-7-06(Late News)]Time-Domain Study on Reproducibility of Laser-Based Soft-Error Simulation
○H. Itsuji1,2, D. Kobayashi1,2, N. Lourenco3, K. Hirose1,2(1.Univ. of Tokyo(Japan), 2.ISAS/JAXA(Japan), 3.GTRI(USA))
[B-1-01(Invited)]Operation Mechanism and Novel Functions of Oxide-Based Atomic Switches
○T. Tsuruoka1, T. Hasegawa2, K. Terabe1, M. Aono1(1.NIMS(Japan), 2.Waseda Univ.(Japan))
[B-1-02]Gate Contact RRAM in Nano-scaled FinFET Logic Technologies
○M. Y. Hsu1, Y. D. Chih2, C. J. Lin1, Y. C. King1(1.National Tsing Hua Univ.(Taiwan), 2.TSMC(Taiwan))
[B-1-03]A Sidewall Electrode TiOx/TiOxNy ReRAM with Excellent Memory Window Control and Reliability Using Plasma Oxidation and a Novel Degradation-detecting Writing Algorithm
○D. Lee1, J. Wu1, M. Lee1, E. Lai1, W. Khwa1, Y. Lin1, W. Chen1, K. Chiang1, T. Wang1, S. Horng2, J. Gong2, H. Lung1, K. Hsieh1, C. Lu1(1.Macronix International Co., Ltd.(Taiwan), 2.National Tsing Hua Univ.(Taiwan))
[B-1-04]Switching Mechanism in Resistive Random Access Memory by First-Principles Calculation Using Practical Model Based on Experimental Results
○T. Moriyama1, T. Yamasaki2, S. Hida1, T. Ohno2,3, S. Kishida1,4, K. Kinoshita1,4(1.Tottori Univ.(Japan), 2.NIMS(Japan), 3.Univ. of Tokyo(Japan), 4.Tottori Integrated Frontier Res. Center(Japan))
[B-1-05]Statistical Analysis of the Correlations between Cell Performance and its Initial States in CRRAM Cells
○Y. Kao1, W. Hsieh1, C. Chen2, Y. King1, C. Lin1(1.National Tsing Hua Univ.(Taiwan), 2.TSMC(Taiwan))
[B-2-01(Invited)]Perpendicular STT-MRAM Macro Embedded into 40nm CMOS Logic Platform
○Y. Lu1(1.Hikstor Technology Co., Ltd.(China))
[B-2-02]Study about the Ion Beam Etching (IBE) Process for the High Density Spintronic Devices and its Damage Recovery by the Oxygen Showering Post-treatment (OSP)
○J. Jeong1,2, T. Endoh1,3,4(1.Tohoku Univ.(Japan), 2.Samsung Electronics Co. Ltd(Korea), 3.CIES, Tohoku Univ.(Japan), 4.JST-ACCEL(Japan))
[B-2-03]Highly Reliable MTJ-Based Nonvolatile Logic-in-Memory LSI with Content-Aware Write Error Masking Scheme
○M. Natsui1, A. Tamakoshi1, T. Endoh1, H. Ohno1, T. Hanyu1(1.Tohoku Univ.(Japan))
[B-2-04]A Soft/Write-Error Resilient CMOS/MTJ Nonvolatile Flip-Flop Based on Majority-Decision Shared Writing
○N. Onizawa1, T. Hanyu1(1.Tohoku Univ.(Japan))
[B-2-05]Long-Term Reliable Physically Unclonable Function using Oxide Tunnel Barrier Breakdown on 2T-2MTJ Based Embedded-STT-MRAM
○S. Takaya1, T. Tanamoto1, H. Noguchi1, K. Ikegami1, K. Abe1, S. Fujita1(1.Toshiba Corp.(Japan))
[B-2-06]A Compact and Ultra-Low-Power STT-MRAM-Based Associative Memory for Nearest Neighbor Search with Full Adaptivity of Template Data Format Employing Current-Mode Similarity Evaluation and Time-Domain Minimum Searching
○Y. Ma1, S. Miura1, H. Honjo1, S. Ikeda1, T. Hanyu1, H. Ohno1, T. Endoh1(1.Tohoku Univ.(Japan))
[B-3-01]A Physics-Based Compact Model of Resistive Switching for Bi-layered TaOX-RRAM
○Y. D. Zhao1, P. Huang1, J. J. Hu1, X. Y. Liu1, J. F. Kang1(1.Peking Univ.(China))
[B-3-02]Switching Operation of Double-Layer Conductive Bridging RAM Investigated using In-situ Transmission Electron Microscopy
○M. Arita1, S. Hirata1, A. Takahashi1, T. Hiroi1, M. Jo1, A. Tsurumaki-Fukuchi1, Y. Takahashi1(1.Hokkaido Univ.(Japan))
[B-3-03]Analysis of "hot spot" in Conducting-bridge Random Access Memory (CBRAM) by Impedance Method
○A. Fukushima1, K. Kinoshita1(1.Tottori Univ.(Japan))
[B-3-04]Bipolar and Unipolar Switching Characteristics of GeTe-Sb2Te3 Superlattice iPCM
X. Wang1,○N. Miyata1, K. V. Mitrofanov1, Y. Saito1, P. J. Fons1, A. Kolobov1, J. Tominaga1(1.AIST(Japan))
[B-3-05]Multi-level Operation of a High-speed, Low Power Topological Switching Random-access Memory (TRAM) Based on a Ge Deficient GexTe/Sb2Te3 Superlattice
○H. Shirakawa1, M. Takato1, M. Araidai1,2, T. Ohyanagi3, N. Takaura3, K. Shiraishi1(1.Nagoya Univ.(Japan), 2.JST-CREST(Japan), 3.Hitachi, Ltd.(Japan))
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