[A-1-1]An Investigation on GIDL Mechanism of Program Disturbance in Sub-20nm NAND Flash Memory
Y.J. Jeong1, I. Kim1, D.H. Yoon1, H.Y. Shim1, M.K. Cho1, K.O. Ahn1, J.W. Kim1(1.SK Hynix (Korea))
2013 International Conference on Solid State Devices and Materials
Sep 24 - Sep 27, 2013Hilton Fukuoka Sea Hawk, Fukuoka, Japan
You can search for presentations in this event.
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2013 International Conference on Solid State Devices and Materials
Sep 24 - Sep 27, 2013Hilton Fukuoka Sea Hawk, Fukuoka, Japan
You can search for presentations in this event.
SearchSearch Results(617)
[A-1-2]Abnormal Cell-to-Cell Interference of NAND Flash Memory
Y.J. Kim1, J.G. Kang1, B. Lee2, G.S. Cho2, S.K. Park2, W.Y Choi1(1.Univ. of Sogang, 2.SK Hynix (Korea))
[A-1-3]Possibility of MONOS Type Memory for Long Lifespan Archive Memory
H. Shirakawa1, K. Yamaguchi1, K. Kamiya1, K. Shiraishi1,2(1.Univ. of Tsukuba, 2.Nagoya Univ. (Japan))
[A-1-4]A Novel Approach for the Understanding of the Charge Loss Paths in a SONOS Flash Memory
J.H. Kuo1, Y.H. Ho1, S.S. Chung1(1.National Chiao Tung University (Taiwan))
[A-1-5]A Gate-All-Around Floating-Gate Memory Device with Triangular-Shaped Poly-Si Nanowire Channels
K.H. Lee1, H.C. Lin1,2, T.Y. Huang1(1.National Chiao Tung Univ., 2.National Nano Device Labs. (Taiwan))
[A-2-1]Exploring the atomic structure of copper-doped Gd2O3 for the conductive bridging RAM technology
M. Lontsi Fomena1, P. Blaise1(1.CEA, LETI (France))
[A-2-2]Impact of overshoot current on SET operation of Atom Switch
T. Sakamoto1, M. Tada1, M. Miyamura1, N. Banno1, K. Okamoto1, N. Iguchi1, H. Hada1(1.LEAP (Japan))
[A-2-3]A New Lateral Conductive Bridge Random Access Memory (L-CBRAM) by Fully CMOS Logic Compatible Process
Y.C. Lin1, Y.W. Chin1, M.C. Hsieh1, Y.D. Chih2, K.H. Tsai3, M.J. Tsai3, Y.C. King1, C.J. Lin1(1.National Tsing-Hua Univ., 2.Taiwan Semiconductor Manufacturing Company, 3.Industrial Technology Research Inst. (Taiwan))
[A-2-4]Excellent Scalability Including Self-Heating Phenomena of Vertical-Channel Field-Effect-Diode (FED) Type Capacitorless One Transistor DRAM Cell
T. Imamoto1,2, T. Endoh1,2(1.Tohoku Univ., 2.JST-CREST (Japan))
[A-2-5]Fluorine ion implantation optimization in Saddle-Fin array devices for sub-40-nm DRAM technology
K.L. Chiang1,2, W.P. Lee1,2, C.C. Lee1, C.S. Sung1, C.K. Wei1,2, C.M. Yang1,2, J.C. Wang2, P. Kao1, C.Y. Lee2, H.H. Chen1, C.Y. Hsiao1, C.S. Lai2(1.Chang Gung Univ., 2.Inotera Memories Inc. (Taiwan))
[A-3-1]Carrier Injection Induced Switching of Supper-lattice GeTe/Sb2Te3 Phase Change Memories
S. Kato1, M. Araidai1, K. Kamiya1, T. Yamamoto1, K. Shiraishi1, T. Ohyanagi2, N. Takaura2(1.Univ. of Tsukuba, 2.Low-power Electronics Association & Project (Japan))
[A-3-2]Chemical Vapor Deposition GeTe/Sb2Te3 Super-Lattice Phase Change Memory
M. Kitamura1, T. Morikawa1, T. Ohyanagi1, M. Tai1, M. Kinoshita1, K. Akita1, N. Takaura1(1.Low-power Electronics Association and Project (Japan))
[A-3-3]Investigation of Multi-Level-Cell Operation with 2-Step SET Pulse and SET Operation on Super-Lattice Phase Change Memories
T. Egami1, K. Johguchi1, S. Yamazaki1, K. Takeuchi1(1.Chuo Univ. (Japan))
[A-3-4]A New Insight on IRESET Reduction of Carbon-doped GST based PCM
Q. Hubert1,2, C. Jahan1, V. Sousa1, L. Perniola1, A. Kusiak3, J.L. Battaglia3, P. Noé1, M. Bernard1, C. Sabbione1, M. Tessaire1, F. Pierre1, P. Zuliani4, R. Annunziata4, G. Pananakakis2, B. De Salvo1(1.CEA - LETI, Minatec Campus, 2.IMEP - LAHC, 3.Lab. I2M, Univ. de Bordeaux, 4.STMicroelectronics (France))
[A-4-1]A Novel High-Density Embedded AND-type Spilt Gate Flash Memory
W.C. Shen1, H.W. Pan1, Z.S. Yang1, Y.D. Chih2, T.L. Lee1, C.W. Lien1, Y.C. King1, C.J. Lin1(1.National Tsing Hua Univ., 2.Taiwan Semiconductor Manufacturing Company (Taiwan))
[A-4-2]A Logic CMOS Process Compatible Two-Bit MTP SONOS Nonvolatile Memory
C.T. Tsai1, H.T. Wang1, C.H. Chou1, Y.H. Ho1, S.S. Chung1, W. Chang2, S.D. Wang2, C.H. Chen2(1.National Chiao Tung University, 2.UMC (Taiwan))
[A-4-3]Experimental Study of 3D Fin-Channel Charge Trapping Flash Memories with TiN Metal and Poly-Si Gates
Y.X. Liu1, T. Matsukawa1, K. Endo1, S. O'uchi1, J. Tsukada1, H. Yamauchi1, Y. Ishikawa1, W. Mizubayashi1, Y. Morita1, S. Migita1, H. Ota1, M. Masahara1(1.AIST (Japan))
[A-4-4]Investigation of Random Grain-Boundary Induced Variability for Stackable NAND Flash Using 3D Voronoi Grain Patterns
C.W. Yang1, P. Su1(1.National Chiao Tung Univ. (Taiwan))
[A-5-1]Optimum Crystal Orientation in Rhombohedral PZT Films for FeRAM Application
H. Funakubo1, Y. Ehara1, T. Oikawa1, T. Yamada2,3, S. Utsugi1(1.Tokyo Inst. Tech., 2.Nagoya Univ., 3.JST (Japan))
[A-5-2]Organic ferroelectric gate FET memory using high-mobility rubrene thin film
T. Kanashima1, Y. Katsura1, M. Okuyama2(1.Osaka Univ., 2.Osaka Univ. (Japan))
[A-5-3]A New 28nm HKMG CMOS Logic OTP Cell
W.Y. Hsiao1, C.Y. Mei1, W.C. Shen1, Y.D. Chih2, Y.C. King1, C.J. Lin1(1.National Tsing-Hua Univ., 2.Taiwan Semiconductor Manufacturing Company (Taiwan))
[A-6-1]Modeling of Transition Metal Oxide Based RRAM Devices
J.F. Kang1, B. Gao1, B. Chen1, P. Huang1, X.Y. Liu1(1.Peking Univ. (China))
[A-6-2]Conducting filament engineering by triple-layer RRAM for uniform resistive switching
D. Lee1, J. Park1, S. Park2, J. Woo1, E. Cha1, S. Lee1, Y. Koo1, K. Moon1, J. Song1, H. Hwang1(1.Pohang Univ. of Sci. and Tech., 2.Gwangju Inst. of Sci. and Tech. (Korea))
[A-6-3]Improvement of Cycling Disturbance and Yield Enhancement of ReRAM using Susceptibility-Aware Write
S.Y. Kim1,2, J.M. Baek1, D.J. Seo1, J.K. Park1, J.H. Chun1, K.W. Kwon1(1.Sungkyunkwan Univ., 2.Memory Division, Samsung Electronics Corp. Ltd. (Korea))
[A-6-4]Mb-Class Array Level Investigation of Program Verify Methods for ALxOy ReRAM
S.Y. Ning1,2, T.O. Iwasaki1, K. Takeuchi1(1.Chuo Univ., 2.Univ. of Tokyo (Japan))
[A-7-1]Physics in Charge Injection Induced On-Off Switching Mechanism of Oxide-Based Resistive Random Access Memory (ReRAM) and Superlattice GeTe/Sb2Te3 Phase Change Memory (PCM)
K. Shiraishi1,2, M.Y. Yang1, S. Kato1, M. Araidai3, K. Kamiya1, T. Yamamoto1, T. Ohyanagi4, N. Takaura4, M. Niwa5, B.M. Kope6, Y. Nishi6(1.Univ. of Tsukuba, 2.Nagoya Univ., 3.Univ. of Tsukuba, 4.Low-power Electronics Association & Project, 5.Tohoku Univ., 6.Stanford Univ. (Japan))
[A-7-2]A Novel Self-rectifying WSixOy Device in a Double-density Architecture for 3D ReRAM
D.Y. Lee1, E.K. Lai1,2, W.C. Chien1, M.H. Lee1, F.M. Lee1, Y.C. Chen1, S.F. Horng2, J. Gong2, Y.K. Huang1, H.H. Hsu1, Y.T. Huang1, C.C. Yu1, H.L. Lung1, K.Y. Hsieh1, C.Y. Lu1(1.Macronix Int'l Corp., Ltd., 2.National Tsing Hua Univ. (Taiwan))
[A-7-3]Study on nano-scale threshold switching behavior of NbOx film for ReRAM selector application
Y.M. Koo1, Y.H. Choi1, E.J. Cha1, D.S. Lee1, J.Y. Woo1, J.H. Song1, K.B. Moon1, J.S. Park1, S.H. Lee1, H.S. Hwang1(1.Pohang Univ. of Sci. and Tech. (Korea))
[A-7-4]Excellent Reliability and Switching Uniformity of RRAM by Optimizing SET/RESET Pulse Shape to Minimize Current Overshoot
J.H. Song1, D.S. Lee1, J.Y. Woo1, Y.M. Koo1, E.J. Cha1, S.H. Lee1, J.S. Park1, K.B. Moon1, H.S. Hwang1(1.Pohang Univ. of Sci. and Tech. (Korea))
[A-8-1]Metal Oxide RRAM For Next Generation Mass Storage: 3D Vertical Architecture and Electrode/Oxide Interface Engineering
H.Y. Chen1, S. Yu1, B. Gao2, Y. Deng2, P. Huang2, H. Tian3, Z. Jiang1, Y. Wu1, T. Ren3, J.F. Kang2, H.S.P. Wong1(1.Stanford Univ., 2.Peking Univ., 3.Tsinghua Univ. (USA))
[A-8-2]The Impact of Bending and Light Exposure on the Resistive Switching Characteristics of Transparent Flexible ITO/ZnO/ITO Resistive RAM (RRAM)
C.L. Lin1, Y.H. Yang1, C.M. Wu1, P.C. Juan2, C.H. Soh1, Y.L. Huang1, W.Y. Chang1(1.Feng Chia Univ., 2.Mingchi Univ. of Tech. (Taiwan))
[A-8-3]High Performance Oxide Diode
I..P. Radu1,2, B. Govoreanu1, M.R. Ikram1,2, A.P. Peter1, K. Martens1,2, H. Hody1, W. Kim1, M. Toeller3, V. Paraschiv1, P. Favia1, S. Clima1, S. De Gendt1,2, M. Heyns1,2, A. Stesmans2, M. Jurczak1(1.imec, 2.Univ. of Leuven, 3.Tokyo Electron Ltd. (Belgium))
[A-8-4]Pulsed Operation of Resistance Switching Memory of Si/CaF2/CdF2 Resonant-tunneling Quantum-well Structures
J. Denda1, K. Suda1, Y. Kuwata1, M. Watanabe1(1.Tokyo Inst. of Tech. (Japan))
[B-1-2]Thermal and Plasma Treatments for Improved (Sub-)1nm EOT Planar and FinFET-based RMG High-k Last Devices and Enabling a Simplified Scalable CMOS Integration Scheme
A. Veloso1, G. Boccardi1, L.A. Ragnarsson1, Y. Higuchi2, H. Arimura1,3, J.W. Lee1,3, E. Simoen1, M.J. Cho1, Ph.J. Roussel1, V. Paraschiv1, X. Shi1, T. Schram1, S.A. Chew1, S. Brus1, A. Dangol1, E. Vecchio1, F. Sebaai1, K. Kellens1, N. Heylen1, K. Devriendt1, H. Dekkers1, A. Van Ammel1, T. Witters1, T. Conard1, I. Vaesen1, O. Richard1, H. Bender1, R. Athimulam1, A. Thean1, N. Horiguchi1(1.Imec, 2.Panasonic, 3.K. U. Leuven (Belgium))
[B-1-3]Si:C-S/D Engineering using Cascade C7Hx Implantation Followed by Rapid Solid-Phase Epitaxy and Laser Annealing for nMOSFET with Highly-Strained and Low-Resistive S/D
T. Yamaguchi1, Y. Kawasaki1, T. Yamashita1, Y. Nishida1, M. Mizuo2, K. Maekawa1, M. Fujisawa1(1.Renesas Electronics Corp., 2.Renesas Semiconductor Engineering Corp. (Japan))
[B-1-4]Impact of Additional Pt on Channel Stress Induced by NiSi Film Formation
M. Mizuo1, T. Yamaguchi2, S. Kudo2, Y. Hirose1,2, H. Kimura2, J. Tsuchimoto2, N. Hattori2(1.Renesas Semiconductor Engineering Corp., 2.Renesas Electronics Corp. (Japan))
[B-2-1]Low-temperature Microwave Annealing Process for Ge MOSFETs
Y.J. Lee1,6, S.S. Chuang2, C.I. Liu3, F.K. Hsueh1, P.J. Sung1, C.T Wu1, C.H. Lai4, Y.M. Wan3, M.I. Current5, T.Y. Tseng2(1.National Nano Device Lab., 2.National Chiao Tung Univ., 3.I-Shou Univ., 4.Chung Hua Univ., 5.Current Scientific, 6.National Chung Hsing Univ. (Taiwan))
[B-2-2]Low NiGe Contact Resistances by Carrier Activation Enhancement (CAE) Techniques for Ge CMOSFETs
H. Miyoshi1, T. Ueno1, Y. Hirota1, J. Yamanaka2, K. Arimoto2, K. Nakagawa2, T. Kaitsuka1(1.Tokyo Electron Ltd., 2.Univ. of Yamanashi (Japan))
[B-2-3]Formation of Epitaxial Nickel Monogermanide on Ge(100) by Annealing of Ni/Sn Bilayer
M. Koike1, Y. Kamimuta1, Y. Moriyama1, Y. Kamata1, E. Kurosawa1, T. Tezuka1(1.AIST (Japan))
[B-2-4]Epitaxial Nickel Distanogermanide [Ni(Ge1-xSnx)2] Contact Formation using Pulsed Laser Annealing
X. Xu1, W. Wang1, Y. Dong1, E.Y.J. Kong1, X. Gong1, Q. Zhou1, G. Han1, P. Guo1, L. Wang1, Y.C. Yeo1(1.National Univ. of Singapore (Singapore))
[B-3-1]3D dopant analysis in nano scale devices (FinFETs) by Atom Probe Tomography
A.K. Kambham1,2, A. Kumar1,2, W. Vandervorst1,2(1.Katholieke Univ. Leuven, 2.IMEC (Belgium))
[B-3-2]Deterministic placement of doping atoms on hydroxylated surfaces
L. Mathey1,2,3, L. Veyre1, H. Fontaine2, V. Enyedi2, K. Yckache2, J. Guerrero2, N. Chevalier2, F. Martin2, J.P. Barnes2, F. Bertin2, C. Durand4, M. Berthe4, B. Grandidier4, C. Thieuleux1, C. Coperet1,5(1.C2P2, CPE Lyon, 2.CEA-LETI, 3.Osaka Univ., 4.IEMN, 5.ETH Zurich (France))
[B-3-3]Size and Stress Effects in Ultraviolet Raman Spectra of Few-Nanometer-Thick SOI Nanofilms and Single Nanowires for Future CMOS Devices
V.D. Poborchii1, T. Tada1, Y. Morita1, S. Migita1, T. Kanayama1, P. Geshev2(1.National Institute of Advanced Industrial Science and Tech., 2.Inst. of Thermophysics of the Russian Academy of Sciences (Japan))
[B-4-1]Detection of oxidation-induced compressive stress in Si(100) substrate near the SiO2/Si interface with atomic-scale resolution
T. Suwa1, K. Nagata2, H. Nohira3, K. Nakajima4, A. Teramoto1, A. Ogura2, K. Kimura4, T. Muro5, T. Kinoshita5, S. Sugawa1, T. Hattori1, T. Ohmi1(1.Tohoku Univ., 2.Meiji Univ., 3.Tokyo City Univ., 4.Kyoto Univ., 5.JASRI (Japan))
[B-4-2]Layer-by-Layer GeO2 Formation in the Self-Limited Oxidation Regime of Ge
C.H. Lee1,2, T. Nishimura1,2, T. Tabata1,2, K. Nagashio1,2, A. Toriumi1,2(1.Univ. of Tokyo, 2.JST-CREST (Japan))
[B-4-3]Modified Deal-Grove model for the thermal oxidation of Ge and Al2O3 capped Ge
S.K. Wang1, X.L. Wang1, L. Han1,2, W. Zhao1, B. Sun1, W.W. Wang.1, C. Zhao1, H.G. Liu1(1.Inst. of Microelectronics, Chinese Academy of Sciences, 2.Southeast University (China))
[B-5-1]Thermodynamic consideration and experimental demonstration for solving the problems of GeO2 solubility in H2O and GeO desorption from GeO2/Ge
C. Lu1,2, C.H. Lee1,2, W.F. Zhang1,2, T. Nishimura1,2, K. Nagashio1,2, A. Toriumi1,2(1.Univ. of Tokyo, 2.JST-CREST (Japan))
[B-5-2]Charge neutrality level shift in the Bardeen limit of Fermi-level pinning at atomically flat Ge/metal interface
T. Nishimura1,2, T. Nakamura1, T. Yajima1,2, K. Nagashil1,2, A. Toriumi1,2(1.The Univ. of Tokyo, 2.JST-CREST (Japan))
[B-5-3]Interaction of Sn atoms with Defects Introduced by Ion Implantation in Ge Substrate
T. Arahira1, M. Fukudome1, N. Taoka1, W. Takeuchi1, M. Sakashita1, O. Nakatsuka1, S. Zaima1(1.Nagoya Univ. (Japan))
[B-6-1]Germanium-Tin Tunneling Field-Effect Transistor: Device Design and Experimental Realization
Y. Yang1, P. Guo1, W. Wang1, X. Gong1, L. Wang1, K.L. Low1, G. Han1, Y.C. Yeo1(1.National Univ. of Singapore (Singapore))
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