[OP-01]Welcome Address
Toshiro Hiramoto (Chair, Organizing Committee)
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1969 - 2025
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[OP-02]Welcome Address
Tsunenobu Kimoto (President, The Japan Society of Applied Physics)
[AW]Award Ceremony
[PL-01 (Plenary)]Molecular engineering of interfaces for high performance perovskite solar cells
〇Tsutomu Miyasaka1(1. Toin University of Yokohama)
[PL-02 (Plenary)]Present and Future Challenges of HBM
〇Myeong-Jae Park1(1. SK hynix)
[PL-03 (Plenary)]The Science Policy of France and Japan collaboration through CNRS
〇Bruno Le Pioufle1(1. CNRS Office for North-East Asia)
[A-1-01 (Invited)]Modeling of Transistor and Interconnect Technologies Targeting Next Generation Logic GAA and CFET Nodes
〇Ashish Pal1, Pratik B. Vyas1, Gregory Costrini1, El Mehdi Bazizi1(1. AMAT (United States of America))
[A-1-02]Ultimate Scaling of the Bonding Dielectric for sequential CFET
〇ANNE VANDOOREN1, Kevin Vandersmissen1, Ferenc Fodor1, Gerhard Bast2, Jeffrey Mileham2, Steven Demuynck1, Katia Devriendt1, Naoto Horiguchi1, Serge Biesemans1(1. imec (Belgium), 2. KLA Corporation (United States of America))
[A-1-03]Recent insights in direct extraction of access resistance components in NSFET and CFET devices with the cascaded transistor method
〇PIERRE CHARLES EYBEN1, Andrea Pondini1,2, Hiroaki Arimura1, Thomas Chiarella1, Hans Mertens1, Clément Porret1, Erik Rosseel1, Ritam Sarkar1, Maryam Hosseini1, Daisy Zhou1, Jérome Mitard1, Naoto Horiguchi1(1. IMEC (Belgium), 2. KU Leuven (Belgium))
[A-1-04]Comparative Analysis of Conventional and Line-Type Tall Via Structures for CFET: Performance, Scalability, and Process Feasibility
〇Jimyoung Lee1,2, Seung Kyu Kim1,2, KwangYoung Lee1,2, Jongwook Jeon1(1. Sungkyunkwan Univ. (Korea), 2. Samsung Electronics (Korea))
[A-1-05]Evaluation of SiCO as a Protective Layer for Nanosheet Integrity and Random Parasitic Channel Mitigation in Monolithic Complementary FET Fabrication
〇Yu-Fan (Andy) Peng1, Steven Demuynck1, Camila Toledo de Carvalho Cavalcante1, Jishnu Ganguly1, Cassie Sheng1, Karen Stiers1, Anne Vandooren1, Maryam Hosseini1, Dmitry Batuk1, Thomas Chiarella1, Anthony Peter1, Maria Chistiakova1, Alfonso Marquez1, Lucas PetersenBarbosa Lima1, Naoto Horiguchi1, Serge Biesemans1(1. IMEC (Belgium))
[A-1-06]Defect Characterization through Fin and Gate Modules for Complementary Field-Effect Transistor Fabrication
〇Xiuju Zhou1, Nachiketa Zhou Janardan1, Andrea Mingardi1, Ataklti Weldeslassie1, Anabela Veloso1, Lucas Petersen Barbosa Lima1, Serge Biesemans1, Kaushik Sah2, Roel Gronheid2, Andrew Cross2(1. IMEC (Belgium), 2. KLA Corp. (United States of America))
[A-2-01]Vt Fine-Tuning for Multi-Vt using Wet Fine-Etching of LaO in Dipole-first
〇Hikaru Kawarazaki1, Ju-Geng Lai4, Hiroaki Arimura4, Leo Lukose4, Dai Ueda1, Stephan Brus4, Yukifumi Yoshida2, Takayoshi Tanaka2, Yoichi Tanaka3, Koji Nakata3, Yuuichi Ogawa3, Nobuko Gan3, Hideaki Iino3, Min-Soo Kim4, Naoto Horiguchi4, Naveen Reddy4, Efrain Altamirano Sanchez4(1. SCREEN SPE Germany GmbH (Germany), 2. SCREEN Semiconductor Solutions Co., Ltd. (Japan), 3. Kurita Water Industries Ltd. (Japan), 4. imec (Belgium))
[A-2-02]Fluorine-Compatible Dipole-First Gate Stack with Yttrium Oxides for Multi-Vth and Enhanced Device Performance
〇Sangkuk Han1, Kyungsoo Park1, Wonjae Choi1, Wonyoung Jang1, Haesoo Jang1, Kyungwook Park1, Changhwan Choi1(1. Hanyang University (Korea))
[A-2-03]Threshold Voltage Design for GAAFETs through Work Function Metal Thickness Engineering under Tight Nanosheet Spacing
〇Hiroyuki Ota1, Yukinori Morita1, Kenzo Manabe1, Misako Morota1, Naoya Okada1, Shinji Migita1, Yoshihiro Hayashi1(1. AIST (Japan))
[A-2-04]Density Functional Theory Analysis of Vt and CMOS Polarity Control in Si High K based FETs
〇John Robertson1, Ruyue Cao1,2, Jun-Wei Luo2, Hailing Guo1, Yuzheng Guo3(1. Cambridge University (UK), 2. CAS (China), 3. Wuhan University (China))
[A-2-05]Mechanism of Fluorine-induced Suppression of Effective Work Function Lowering in TiN/TiAlC Metal Gate Electrodes
〇Kenzo Manabe1, Kazuya Uejima1, Hiroyuki Ota1, Yukinori Morita1, Atsushi Yagishita1, Toshifumi Irisawa1, Yoshihiro Hayashi1(1. AIST (Japan))
[A-2-06]Flat-Band Voltage Tuning through Al Layer Position Engineering
〇Wonjae Choi1, Sangkuk Han1, Wonyoung Jang1, Haesoo Jang1, Jaewon Chung1, Kyungwook Park1, Changhwan Choi1(1. Hanyang University (Korea))
[A-3-01]Interface trap density evaluation of off-angle Si(110)/SiO2 interface:Toward understanding of interface properties in advanced MOSFET
〇Ryotaro Shimura1, Eishin Nako1, Koji Matsumoto2, Akihiro Suzuki2, Hiroaki Yamamoto2, Kazuhito Matsukawa2, Mitsuru Takenaka1, Shinichi Takagi1, Kasidit Toprasertpong1(1. The Univ. of Tokyo (Japan), 2. SUMCO Corp. (Japan))
[A-3-02]Unveiling Ferroelectric Properties of Co-Injected ALD HfxZr1-xO2: A Study of Thickness, Composition, and Cryogenic Behavior (73 to 300 K)
〇Kyungsoo Park1, Minhyuk Kim1, Chulwon Chung1, Sunbum Kim1, Sangkuk Han1, Changhwan Choi1,2(1. Division of Materials Science and Engineering, Univ. of Hanyang (Korea), 2. Department of Semiconductor Engineering, Univ. of Hanyang (Korea))
[A-3-03]Ti-Based Spacer Approach for Semi-Damascene Spacer-is-Dielectric SADP Process Integration at MP18 Demonstration
〇Vincent Renaud1, Gilles Delie1, Debanjan Jana2, Yiting Sun2, Miguel De Abreu Neto3, Sungdae Woo4, David De Roest2, Hyungjoo Shin4, Andrey Sokolov4, Daniele Piumi2, Laurent Souriau1, Chen Wu1, Seongho Park1, Zsolt Tokei1(1. Imec (Belgium), 2. ASM Belgium (Belgium), 3. ASM Japan (Japan), 4. ASM Korea (Korea))
[A-3-04]Effective Deep Learning Technology for Predicting High-Aspect Ratio Contact Hole Striation Problem in 3D V-NAND Flash Memory
〇BYUNG YONG CHOI1, HOYUN JUNG1, JONGIK HONG1, YOUNGCHAN PARK1, BONG-TAE PARK1, SEUNGWAN HONG1, SUNG HOI HUR1(1. Samsung Electronics Co., Ltd. (Korea))
[A-3-05]Accurate Si3N4 Wet Etching Rate Prediction with Small Training Data by Gaussian Process Regression
〇Yusuke Hirata1, Koki Shibata1, Naoko Misawa1, Takashi Ota3, Yuki Yoshinaga3, Chihiro Matsui1, Ken Takeuchi1,2(1. Department of Electrical Eng. and Info. Systems, The Univ. of Tokyo (Japan), 2. Systems Design Lab., Graduate School of Eng., The Univ. of Tokyo (Japan), 3. Cleaning Equipment Development Operations, SCREEN Semiconductor Solutions Co., Ltd. (Japan))
[A-3-06]Characterization of Plasma-induced Damage on TiN/HfO2/SiO2 Stacked Structure during Multi-Vt Process Using Different Gas Chemistries
〇Hidefumi Hirabayashi1, Satoshi Sakai1, Kiyohiko Sato1, Naoyuki Kofuji1, Makoto Miura1(1. Hitachi High-tech Corporation (Japan))
[A-4-01 (Invited)]Cryogenic characterization of advanced FDSOI devices for quantum computing applications
〇Bruna Cardoso Paz1, Giselle Elbaz1, Johan Pelloux-Prayer1, Pierre-Louis Julliard1, Mathilde Ouvrier-Buffer2, Mikaël Cassé3, Flavio Bergamaschi3, Baptiste Jadot3, Mathieu Darnas3, Renan Lethiecq1, Gregoire Roussely3, Heimanu Niebojewski3, Benoit Bertrand3, Brian Martinez3, Gerard Billiot3, Franck Badets3, Tristan Meunier1, Maud Vinet1(1. Quobly (France), 2. CNRS Institut Néel (France), 3. CEA-Leti (France))
[A-4-02]Anomalous Variability of Subthreshold Characteristicsin Bulk and SOI MOSFETs at a Cryogenic Temperature
〇Tomoko Mizutani1, Kiyoshi Takeuchi1, Takuya Saraya1, Takumi Inaba2, Hidehiro Asai2, Hiroshi Oka2, Takahiro Mori2, Masaharu Kobayashi1, Toshiro Hiramoto1(1. The University of Tokyo (Japan), 2. AIST (Japan))
[A-4-03]Planar FD-SOI NFETs with Ultra-Thin Si Body: Device Process Integration
〇Dmitry Batuk1, Sylvain Baudot1, Tom Schram 1, Erik Rosseel1, Aryan Afzalian1, Anish Dangol1, An De Keersgieter1, Anne Vandooren1, Farid Sebaai1, Mohamed Saib1, Emma Vecchio1, Subhobroto Choudhury1, Bianca Chou1, Naoto Horiguchi1, Paul Heremans1(1. imec (Belgium))
[A-4-04]Strain and Mobility Enhancement in SiGe-OI pMOSFETs by Low O2 Pressure Ge Condensation
〇Ke Zhou1, Ruocheng Yang1, Junkang Li1,2, Rui Zhang1,2(1. College of Integrated Circuits, Zhejiang University (China), 2. Zhejiang ICsprout Semiconductor Company Ltd. (China))
[A-4-05]Evaluation of Transient Characteristics on Steep Subthreshold Slope “Gate-Controlled Carrier-Injection SOI-Transistor”
〇Haruki Yonezaki1,2, Takayuki Mori1, Jiro Ida1(1. Kanazawa Inst. of Tech. (Japan), 2. KIOXIA Corp. (Japan))
[A-5-01 (Invited)]Challenges and Opportunities in CFET-Based SRAM Design
Yu-Cheng Lu1, Meng-Lin Wu1, Amit Ranjan Trivedi2, 〇Vita Pi-Ho Hu1(1. National Taiwan Univ. (Taiwan), 2. Univ. of Illinois at Chicago (United States of America))
[A-5-02]A Simulation Study of Single Event Upset in Nanosheet-based CFET SRAM
〇Vanness Filbert Cierra1, Sida Wang1, Yoshinari Kamakura1(1. Osaka Institute of Technology (Japan))
[A-5-03]Stacked Transistors with Nanosheet-based Flip FET for A10 Node: A DTCO Viewpoint
〇Haoran Lu1, Jingru Jiang1, Jiacheng Sun1, Ming Li1, Runsheng Wang1, Heng Wu1(1. Peking Univ. (China))
[A-5-04]Alleviating Self-Heating-Effect in DFF by Introducing Equivalent Circuit in Double-Cell-Height CFET Design
〇Liang-Chi Huang1, Huei-Lin Shih1, Xiang-Ting Huang1, Pen-Yi Chu1, Bo-Hsun Juan1, Ko-Cheng Lu1, Tzu-Hsuan Chang1(1. National Taiwan Univ. (Taiwan))
[A-5-05]Effect of an Additional Top Silicon Substrate on Mitigating
Self-Heating Effect in Complementary FET (CFET)
〇Seung Kyu Kim1,2, Johyeon Kim1, Kee-Won Kwon1, Jongwook Jeon1(1. Sungkyunkwan Univ. (Korea), 2. Samsung Electronics Corp. (Korea))
[A-6-01 (Invited)]Oxide Semiconductors for Future DRAM and Monolithic 3D Integration
Kexin Wang1, 〇Jianshi Tang1(1. Tsinghua Univ. (China))
[A-6-02]Laser annealing technology for storage node contact in graphic DRAMs
〇Dongkyu Jang1, Jieun Lee1, Taehoon Park1, Chanho Park1, Hyodong Ban1(1. Samsung Electronics (Korea))
[A-6-03]Room temperature operation of Ge1−xSnx/Ge1−x−ySixSny resonant tunneling diode
〇Shota Torimoto1, Shuto Ishimoto1, Yoshiki Kato1, Mitsuo Sakashita1, Masashi Kurosawa1, Osamu Nakatsuka1,2, Shigehisa Shibayama1(1. Grad. Sch. of Eng., Nagoya Univ. (Japan), 2. IMaSS, Nagoya Univ. (Japan))
[A-6-04]Agile Prototyping of AI Hardware LSIs Using Multi-Layer Aluminum Interconnects in a Minimal Fab Environment
〇Hirofumi Sumi1, Hideharu Amano1, Naonobu Shimamoto1, Atsutake Kosuge1, Yukinori Ochiai1, Tohru Mogami1, Yoshio Mita1, Makoto Ikeda1(1. The University of Tokyo (Japan))
[A-7-01 (Invited)]Demonstration of single-channel WSe2 CMOS devices and circuits
〇Takamasa Kawanago1(1. AIST (Japan))
[A-7-02]Monolithic 3D CMOS Logic Integration of p-FinFET and 2D n-WSe2 FET with Planar Local Back-Gate
〇Chi-Chun Cheng1, Wen-Yuan Fei1, Ching-Min Hsu1, Po-Wen Chiu1(1. The Univ. of Hsinchu (Taiwan))
[A-7-03]CMOS-Friendly Doping Strategies for p-Type WSe2 Field-Effect Transistors
〇Cheng-Chieh Hsieh1, I-Ling Li1, Cheng-Yang Hsu1, Han-Hsiang Pai1, Tsung-Che Hsieh1, Hung-Hui Yang1, Chien-Wei Chen3, Chih-Chao Yang2, Ying-Hao Chu1, Chao-Hui Yeh1(1. National Tsing Hua Univ. (Taiwan), 2. Taiwan Semiconductor Research Inst. (Taiwan), 3. Taiwan Instrument Research Inst. (Taiwan))
[A-7-04]Fabrication of Electro-Absorption Dual Graphene Modulators on 200 mm Wafer Scale
〇Rasuole Lukose1, Ashraful Islam Raju1, Pawan Kumar Dubey1, Philipp Kulse1, Steffen Marschmayer1, Daniele Capista1, Anna Peczek1, Aleksandra Kroh1, Marco Lisker1,2, Andreas Mai1,2, Mindaugas Lukosius1(1. IHP- Leibniz Institut für innovative Mikroelektronik (Germany), 2. Technical University of Applied Science Wildau (Germany))
[A-8-01]Performance Enhancement Strategies in Vertical FETs for Next-Generation Logics
Zhihao Wang1, 〇Ziqiao Xu1, Yu Liu1, Yanbang Chu1, Chuan Lan1, Yimeng Wang1, Runsheng Wang1, Ming Li1, Heng Wu1(1. Peking University (China))
[A-8-02]Exploration and Insights into Vertical Nanowire/sheet FETs for Ultimate Scaled Circuits/Systems
〇Anabela Veloso1, Bjorn Vermeersch1, Abderrahim Tahiat2, Philippe Matagne1, Adrian Chasin1, Barry OSullivan1, Ruben Asanovski1, Bogdan Cretu2, Eddy Simoen3, Roger Loo1,3, Jeroen Scheerder1, Claudia Fleischmann1,4(1. Imec (Belgium), 2. Normandy Univ., ENSICAEN, UNICAEN, CNRS, GREYC (France), 3. Ghent Univ. (Belgium), 4. KU Leuven (Belgium))
[A-8-03]Trimmable Via Pin Array Capacitor in Fully Compatible CMOS Logic Process in 16nm FinFET Platform
〇Wei-Hwa Lin1, Jian-Yu Wang1, Yue-Der Chih2, Yih Wang2, Jonathan Chang2, Ya-Chin King1, Chrong Jung Lin1(1. Inst. of Electronics Engineering, National Tsing Hua Univ. (Taiwan), 2. Design Technology Platform, Taiwan Semiconductor Manufac. Company (Taiwan))
[A-8-04]Demonstration of Field Curvature Aberration Correction Using Concave Curved Color CMOS Image Sensors
〇Masahide Goto1, Shigeyuki Imura1, Hiroto Sato1(1. NHK Sci. & Tech. Res. Labs. (Japan))
[B-1-01 (Invited)]Horizontal Channel Flash to Explore the Limits of 3D Flash Memory
〇Minoru Oda1, Kosuke Sakamawari1, Shunichi Seno1, Yuki Nakata1, Ryo Fukuoka1, Haruka Kusai1, Keiji Hosotani1, Toru Nakanishi1, Daisuke Hagishima1, Toshiya Ishikawa1, Tatsuo Ogura1, Shinya Naito1, Takashi Kurusu1, Sumiko Mano1, Tsuyoshi Ogikubo1, Motohiko Fujimatsu1, Kikuko Sugimae1, Mina Hatakeyama1, Yuki Inuzuka1, Yusuke Niki1, Rieko Tanaka1, Noboru Shibata1, Hiroshi Nakamura1, Makoto Fujiwara1, Koji Matsuo1, Yoshiro Shimojo1, Fumitaka Arai1, Masaki Kondo1, Tomohiro Oki1, Masaru Kito1(1. Kioxia Corp. (Japan))
[B-1-02]Area Selective Deposited SiN for Confined Charge Trap Layer in 3D NAND Devices
〇Sana Rachidi1, Laurent Breuil1, Silvia Armini1, Yoshitomo Hashimoto2, Daigo Yamaguchi2, Kimihiko Nakatani2, Jie Li1, Marta Coelho Silva1, Geert Van den Bosch1, Maarten Rosmeulen1,3(1. imec (Belgium), 2. KOKUSAI ELECTRIC CORPORATION (Japan), 3. KU Leuven (Belgium))
[B-1-03]Optimizing Cell Structure to Improve Cell Characteristics in IGZO Channel-Based 3D NAND Flash with p-Type Gate
Daewoong Kang1, 〇Sungho Park1,2, Joohyo Kim1,2, Nayoon Kang1,3, Jeongnam Youn1, Youngho Jung4(1. Seoul National University (Korea), 2. Chung-Ang University (Korea), 3. Soongsil University (Korea), 4. Daegu University (Korea))
[B-1-04]A Novel Structure using p-Doped Polysilicon for Wide Memory Window in ferroelectric 3D NAND Flash
Daewoong Kang1, 〇Nayoon Kang1,2, Sungho Park1,3, Joohyo Kim1,3, Jeongnam Youn1, Youngho Jung4(1. Seoul National University (Korea), 2. Soongsil University (Korea), 3. Chung-Ang University (Korea), 4. Daegu University (Korea))
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