Session Details
[PS-01]01: Advanced CMOS: Material Science / Process Engineering / Device Technology
Tue. Sep 3, 2024 3:00 PM - 5:00 PM JST
Tue. Sep 3, 2024 6:00 AM - 8:00 AM UTC
Tue. Sep 3, 2024 6:00 AM - 8:00 AM UTC
Poster Hall (Exhibition Hall A)(1st Floor)
[PS-01-01]A Novel Self-Aligned Backside Contact Architecture for Advanced Logic Nodes
〇QingPeng Wang1, Sumant Sarkar2, TaeYeon Oh3 (1. Lam Research (China), 2. Lam Research (United States of America), 3. Lam Research (Korea))
[PS-01-02]Germanium Gate Stack Fabrication at Low Temperature
using Nonheated Atomic Layer Deposition
〇Taisei Aso1, Hajime Kuwazuru1, Dong Wang1, Keisuke Yamamoto1 (1. Kyushu Univ. (Japan))
[PS-01-03]Logic Cell of CFET Based on Double-Cell-Height to Enhance Intra-Cell Connectivity
〇Liang-Chi Huang1, Pen-Yi Chu1, Ko-Cheng Lu1, Wei-Cheng Kang1, Bo-Hsun Juan1, Tzu-Yin Chen1, Bi-Xian Wu1, Tzu-Hsuan Chang1 (1. National Taiwan University (Taiwan))
[PS-01-04]Performance Evaluation of Cold CFET considering Contact-Placement dependent Gate Resistance Effects
〇Shu-Han Li1, Pin Su1 (1. National Yang Ming Chiao Tung Univ. (Taiwan))
[PS-01-05]Neural Network Prediction of Cryogenic BSIM4 Model Parameters Utilizing a Small Experimental Data Set
〇Takumi Inaba1, Yusuke Chiashi1, Hiroshi Oka1, Minoru Ogura1, Hidehiro Asai1, Shota Iizuka1, Kimihiko Kato1, Shunsuke Shitakata1, Hiroshi Fuketa1, Takahiro Mori1 (1. National Institute of Advanced Industrial Science and Technology (Japan))
[PS-01-06]Reconfigurable-FETs based on CMOS-Compatible Synapse Transistors with inorganic-organic hybrid Methyl-Silsesquioxanes-Based Electrical Double Layer
〇Seung-Hyun Lee1, Won-Ju Cho1 (1. The Univ. of Kwangwoon (Korea))
[PS-01-07]Investigation of Layout Optimization on the Self-heating Effects and Logic Performance of 6T-SRAM Based on Nanosheet and Forksheet FET
〇Pan Zhao1, Tao Yu Zhou1, Nai Qi Liu1, Yan Dong He1, Gang Du1 (1. Peking University (China))
[PS-01-08]Interfacial Trap Density Investigation of HfO2-ZrO2 Superlattice Gate Stacks with Ultra-low Equivalent Oxide Thickness
〇kun zhong1,2,3, Zhaohao Zhang1,2,3, Siyuan Liu1,2,3, Yueyuan Zhang1,2,3, Huaxiang Yin1,2,3 (1. University of Chinese Academy of Sciences (China), 2. Institute of Microelectronics of the Chinese Academy of Sciences (China), 3. Integrated Circuit Advanced Process R&D Center and State Key Laboratory of Fabrication Technologies for Integrated Circuits (China))
[PS-01-09]Charge-Trapping Optoelectronic Memcapacitors Achieving Photoelectric Perception, Storage, and Reconfigurable In-memory Logics
〇Ning Liu1, Siying Zheng2, Jiuren Zhou1,2, Yan Liu1,2, Genquan Han1,2, Yue Hao1 (1. School of Microelectronics, Xidian Univ. (China), 2. Hangzhou Inst. of Tech., Xidian Univ. (China))
[PS-01-10]Effect of Random Potential on Two-dimensional Electronic States
〇Nobuya Mori1 (1. Osaka University (Japan))
[PS-01-11]Comprehensive Study on the Frequency Stability Characteristics of HfO2-ZrO2 Superlattice Ferroelectric Films
〇Qiuxia Wu1, Yue Peng1, Mingshuang Kang1, Chunfu Zhang1, Xiaohua Ma1, Yue Hao1 (1. Wide Bandgap Semiconductor Tech. Disciplines State Key Lab., School of Microelectronics, Xidian Univ. (China))
[PS-01-12]Effect of Non-Uniform Polycrystallinity on Ferroelectric Electrostatic Doped Transistor Variability
〇xinghui wang1, Siying Zheng2, Jiuren Zhou1,2, Hongrui Zhang2, Yan Liu1,2, Yue Hao1,2, Genquan Han1,2 (1. School of Microelectronics, xidian Univ. (China), 2. Hangzhou Inst. of Tech., Xidian Univ. (China))
[PS-01-13]Texture of Orthorhombic ScSi in Annealed TiN / Sc / Si(:P)(001) Contact Stacks
〇Bert Pollefliet1, Clement Porret2, Christophe Detavernier3, Jean-Luc Everaert2, Kiroubanand Sankaran2, Erik Rosseel2, Roger Loo2, André Vantomme1, Clement Merckling1 (1. KU Leuven (Belgium), 2. imec (Belgium), 3. Ghent University (Belgium))
[PS-01-14]AR-HAXPES Evaluation of the Effect of Hydrogen Plasma Treatment on the Chemical Bonding State and Distribution of Hydrogen in SiN Films
〇Yoshiharu Kirihara1, Haruto Omata1, Akira Yasui2, Kiyokazu Nakagawa3, Yuichiro Mitani1, Hiroshi Nohira1 (1. Tokyo City Univ. (Japan), 2. JASRI (Japan), 3. Abit Technologies (Co. Ltd.) (Japan))
[PS-01-15]Analysis of AC Degradation in SiON pMOSFET by Extraction of Threshold Voltage Degradation Profile
〇Donghee Son1, Yeohyeok Yun2 (1. Samsung Electronics (Korea), 2. Korea University of Technology and Education(KOREATECH) (Korea))
[PS-01-16]Atomic-Scale Insights into the Effects of Biaxial Strain on the Electronic Structure of Orthorhombic Hf0.5Zr0.5O2
〇Yu Hong Chen1、Chen You Wei2、Yi Ju Yao2、Fu Ju Hou3、Guang Li Luo3、Yung Chun Wu1,2