[PL-01]Bridging Semiconductor Physics and Nanosheet Device Engineering: From Crystal Anisotropy to Efficient Quantum Transport (tentative)
*Nobuya Mori1(1. The University of Osaka)
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Search Results(228)
[PL-02]Cryogenic CMOS Modeling for Devices and Circuits: The EPFL Cryogenic MOSFET Model Perspective
*Farzan Jazaeri1(1. Swiss Federal Institute of Technology in Lausanne)
[PL-03]From Atom to System: Multi-scale Thermal, Mechanical, and Reliability Modeling of Advanced Packages for AI (tentative)
*Xi-Wei Lin1(1. Synopsys Inc.)
[Session_1-01]From Device Physics to Circuit Co-Design: Multi-Physics Modeling of Monolithic 3D CMOS-NEM Hybrid Circuits
*Woo Young Choi1(1. Seoul National University)
[Session_1-02]Simulation Study on Scaling Limits of Z-direction Pitch in 3D Flash Memories: Toward the Sub-40 nm Regime
*Tatsuo Ogura1, Yuma Hizume1, Yuto Ozeki1, Takayuki Kakegawa1, Hiroshi Takeda1, Takashi Kurusu1, Tomohiro Oki1, Katsuyuki Sekine1(1. KIOXIA Corp.)
[Session_1-03]Vertical Channel-All-Around a-IGZO-FET Towards 2T1D eDRAM Design with Self-Boosted Storage-Node Voltage
*Wenxiang Tang1,2, Xufan Li1,2, Yue Zhao1,2, Xiaoyi Zhang1,2, Qingxiao Zhu1,2, Jingrui Guo3, Lingfei Wang1,2, Ling Li1,2(1. State Key Lab of Fabrication Technologies for Integrated Circuits, Institute of Microelectronics, Chinese Academy of Sciences, 2. University of Chinese Academy of Sciences, 3. School of Information Science and Engineering, Shandong University)
[Session_1-04]Compact Modeling of the Program Saturation Regime in
Charge Trap Flash Memories
*Thomas Hellemans1,2, Devin Verreck1,2, Antonio Arreghini1, Geert Van den bosch1, Maarten Rosmeulen1,2, Michel Houssa2,1, Jan Van Houdt1,2(1. Imec, 2. KU Leuven)
[Session_1-05]Enabling 4F2 DRAM Junctionless Vertical Channel Transistors with Novel Oxygen Inserted Si Substrates – A TCAD Study
*Albert Lu1, Madhav Raj2, Hiu Yung Wong2, Ilya Rumyantsev1, Shuyi Li1, Hideki Takeuchi1(1. Atomera Inc., 2. San Jose State Univ.)
[Session_2-01]Three-Dimensional Quantum Transport in Nanosheet FETs: Effects of Contacts, Geometry, and Multi-Stacks
*Seungjin Lee1, Soyeon Park1, Seunghyun Song2, Mincheol Shin1(1. Korea Advanced Inst. of Sci. and Tech., 2. Samsung Electronics)
[Session_2-02]Alloy-scattering-limited Hole Mobility in SiGe:
First-principles-based Multi-scale Approach
*Gyeongwon Roh1, Yeongjun Lim1, Mincheol Shin1(1. Korea Advanced Inst. of Sci. and Tech.)
[Session_2-03]Framework for Investigating Cryogenic Hole Mobility in Group-IV-Alloy Quantum Wells
*Siddhant Sushil Gangwal1, Shunda Chen2, Tianshu Li2, Michael Povolotskyi3, Dragica Vasileska1(1. Arizona State University, 2. George Washington University, 3. Amentum Solutions)
[Session_2-04]Two-Particle Monte Carlo for TCAD: Fermionic
Treatment of Electron–Electron Scattering
*Josef Gull1, Hans Kosina1(1. TU Vienna, Inst. for Microelectronics)
[Session_2-05]Quantum Transport Simulation Considering Self-Energy for Surface Roughness in Nanosheet FETs
*Sung-Min Hong1, Phil-Hun Ahn2(1. Gwangju Inst. of Sci. and Tech., 2. Korea Advanced Inst. of Sci. and Tech.)
[Session_3-01]Interface Modeling for TCAD Simulations of 2D Semiconductor Transistors
*Akiko Ueda1(1. AIST)
[Session_3-02]Deterministic Full-Band Boltzmann Equation Solver for 2D Materials
*Hendrik Christoph Andre Leenders1, Josephine Faisst1, Christoph Jungemann1(1. RWTH Aachen University)
[Session_3-03]Engineering of n-type Metal-TMD Contacts via Ferroelectric Polarization: an Ab-initio Transport Study
Alessandro Pilotto1, Daniel Lizzit1, *Marco Pala1, David Esseni1(1. Univ. of Udine)
[Session_3-04]Full-Band Semi-Classical Monte Carlo Simulation of Layer Number-Dependent Hole Transport in W- and Mo-Based Transition Metal Dichalcogenides
*Donghyeok Lee1, Sukhyeong Youn1, Yoonhoo Ha2, Jiwon Chang1(1. Yonsei Univ., 2. Samsung Adv. Inst. of Tech., Samsung Electronics Co., Ltd.)
[Session_3-05]Strain-Dependent Electron Transport in Mono-, Bi-, and Trilayer MoS2 and WS2 Using Coupled First-Principles and Full-Band Semi-Classical Monte-Carlo Simulation
*Seongwoo Kang1, Yoonhoo Ha2, Ilgu Yoon1, Jiwon Chang1(1. Yonsei Univ., 2. Samsung Electronics Cop. Ltd.)
[Session_4-01]Efficient Simulation of Gate Leakage Currents in Ultra-scaled Transistors from First Principles
*Mauro Dossena1, Nicolas Vetsch1, Alexander Maeder1, Anders Winka1, Vincent Maillou1, Denghui Lu1, Alexandros Nikolaos Ziogas1, Jiang Cao1, Mathieu Luisier1(1. Integrated System Laboratory (IIS), ETH Zürich, Switzerland)
[Session_4-02]Efficient STEM-EBIC Simulation Using an Adjoint Drift-Diffusion Model
Chenyang Yu1, Sebastian Schneider2, Bernd Rellinghaus2, *Christoph Jungemann1(1. RWTH Aachen Univ., 2. TUD Dresden Univ. of Tech.)
[Session_4-03]Harmonic Balance Boltzmann Equation Solver for Gunn Domains
*Christoph Jungemann1(1. RWTH Aachen University)
[Session_4-04]Challenges of Drift-Diffusion Simulation for Device Characterization at 4.2 K
*Max Renner1, Yu-Chen Chang1, Tobias Linn1, Joachim Knoch1, Christoph Jungemann1(1. RWTH Aachen Univ.)
[Session_4-05]A TCAD-Friendly Numerical Treatment of Bandtails in Cryogenic and Amorphous Oxide Semiconductors
*Mischa Thesberg1, José María González-Medina1, Zlatan Stanojević1, Markus Kampl1, Franz Schanovsky1, Oskar Baumgartner1, Markus Karner1(1. Global TCAD Solutions GmbH)
[Session_5-01]Atomistic Quantum Transport for the Ångström Era
*Philippe Blaise1(1. Silvaco Inc.)
[Session_5-02]SCDMk Wannierization from AO Basis Sets
*Fabian Ducry1, Aryan Afzalian1(1. imec be)
[Session_5-03]Atomistic Insights into NH3 Plasma-Induced Carbon Depletion and Nitrogen Incorporation in SiCOH Low-K Dielectrics
*Sefa Dag1, El Mehdi Bazizi1, Subi Kengeri1, Rohit Gupta1(1. Applied Materials, Inc.)
[Session_5-04]First-Principles Electrostatic Embedding for Dielectric and Capacitance Analysis in Nonequilibrium 2D Devices
*Ryong-Gyu Lee1, Juho Lee1, Yong-Hoon Kim1(1. Korea Advanced Institute of Science & Technology (KAIST))
[Session_5-05]Neural-Network-Based Effective-Mass Hamiltonians for Quantum Transport
*Geunseok Choi1, Jooseok Kim1, Gyeongwon Roh1, Mincheol Shin1(1. KAIST)
[Session_5-06]Thickness-Dependent Conductivity Scaling of B20-Type Chiral Topological Semimetals for Beyond-Cu Interconnect Applications
*Sukhyeong Youn1, HyeukJin Han2, Jiwon Chang1(1. Yonsei Univ., 2. Sungshin Women’s Univ.)
[Session_5-07]DFT-NEGF Modeling of Surface Roughness Scattering in Ultra-Thin-Body Si Nanosheets
*Aryan Afzalian1(1. imec)
[Session_6-01]Unified Lattice Kinetic Monte Carlo Model for Epitaxy, Etch and Reflow Processes for Advanced Semiconductor Device Architectures
*Alexander Schmidt1, Kyungmi Yeom1, Byounghak Lee2, Marton Voeroes2, Hiroyuki Kubotera2, Woosung Choi2, Anthony Payet3, Takeshi Nishimatsu3, Hiroo Koshimoto3, Joohyun Jeon1, Seungmin Lee1, Jaehoon Jeong1(1. Samsung Electronics Co., Ltd, 2. Samsung Semiconductor Inc., 3. Samsung Device Solutions R&D Japan)
[Session_6-02]A First-Principles Study of F2 Selective Etching of Si/SiGe Stacks towards Sub-3 nm Node Transistor Manufacturing
*Qikai Zhao1,2, Junjie Li1, Hua Shao1, Rui Chen1, Lado Filipovic3(1. State Key Lab. of Fabrication Technologies for Integrated Circuits, Institute of Microelectronics, Chinese Academy of Sciences, 2. School of Integrated Circuits, Univ. of Chinese Academy of Sciences, 3. CDL for Multi-Scale Process Modeling of Semiconductor Devices and Sensors, Institute for Microelectronics, TU Wienna)
[Session_6-03]Geometry-Agnostic Feature-Scale PEALD Model
*Philipp Haslhofer1, Tobias Reiter1, Alexander Toifl2, Andreas Hössinger2, Lado Filipovic1(1. Institute for Microelectronics, TU Wien, 2. Silvaco Europe Ltd., Silvaco Inc.)
[Session_6-04]GPU-Accelerated Feature-Scale Process Simulation of CFET Structures
*Tobias Reiter1, Lado Filipovic1(1. Institute for Microelectronics, TU Wien)
[Session_6-05]Surrogate-Assisted Calibration of a DRIE Process Model
*Roman Kostal1, Manuel Kleinbichler3, Stefano Di Nicola4, Lado Filipovic1,2(1. Inst. for Microelectronics, Tech. Univ. Vienna, 2. CDL for Multi-Scale Process Modeling of Semiconductor Devices and Sensors, 3. KAI Kompetenzzentrum Automobil- und Industrieelektronik GmbH, 4. Infineon Technologies Austria AG)
[Session_7-01]Compact Model of Intersubband Coulomb Scattering for FD-SOI Transistors Operating at Cryogenic Temperature
*Miltiadis Alepidis1, Thomas Bédécarrats1, Aurélie Bajolet1, Benjamin Dormieu2, Manohiaina Galal El Dine2, Patrick Scheer2, Issa Sidibe3, Bruna Cardoso Paz3, Sébastien Martinie1(1. Univ. Grenoble Alpes, CEA, Leti, F-38000 Grenoble, France , 2. STMicroelectronics, Crolles, France , 3. Quobly, Grenoble, France)
[Session_7-02]A TCAD-SPICE Simulation Framework for Quantitative Evaluation of MOSFET Properties from SEM Transient Signals
*Yuika Kobayashi1, Yohei Nakamura1, Shinji Yamaguchi2(1. Hitachi, Ltd., 2. Hitachi High-Tech Corp.)
[Session_7-03]PrimeSim D2D: A Scalable, Machine Learning-assisted Data-Driven Modeling Framework for Fast DTCO
*Chien-Ting Tung Tung1, Xiaohan Duan1, Dehuang Wu1, Joddy Wang1(1. Synopsys, Inc.)
[Session_8-01]Device-Consistent Simulation of Spin Exchange Interaction in Quantum Dots Using Green’s-Function Method for Inhomogeneous Dielectric Environments
*Hidehiro Asai1, Shota Iizuka1, Junichi Hattori1, Tsutomu Ikegami1, Takashi Nakayama1, Takahiro Mori1(1. National Institute of Advanced Industrial Science and Technology (AIST))
[Session_8-02]Fast exchange energy simulation in Si spin qubits
for point defect variability assessment
*Pierre-Louis Julliard1, Pericles Philippopoulos2, Tangui Aladjidi1, Kilian Gruel1, Etienne Nowak1, Tristan Meunier1(1. Corp. Quobly, 2. Corp. Nanoacademic)
[Session_8-03]Simulation of Two-qubit Gate Variability and Fidelity of Spin Qubits Built on Nanosheet Technology
*Trung Nguyen1, Sarah Dweik1, Hiu Yung Wong1(1. San Jose State University)
[Session_9-01]Efficient DC Simulation of Monolithic CFETs: A Quasi-1D Approach with Region-Wise Analysis
*Sung-Min Hong1(1. Gwangju Institute of Science and Technology)
[Session_9-02]Impact of 4F2 DRAM Access Transistor Design on Floating Body Effect and Retention
*Ashish Pal1, Lars P. Tatum1, Rohit Gupta1, El Mehdi Bazizi1, Subi Kengeri1(1. Applied Materials)
[Session_9-03]Multiscale Modeling of Channel Surface Roughness: Impact on Front-End-of-Line And Circuit Performance for Advanced Logic Technology
*Ning Yang1, Pratik B. Vyas1, Rohit Gupta1, Ashish Pal1, El Mehdi Bazizi1, Subi Kengeri1(1. Applied Materials Inc.)
[Session_9-04]Impact of Thermal Expansion Mismatch-Induced NMOS Metal Gate Stress on MBCFET Performance
*Sung-Ho Kim1, Sooyoung Park1, Chang Ju Moon1, Jong Su Kim1, Jaehong Lee1, Yoon-Suk Kim1, Seung Hyun Song1, Yonghee Park1, Jaehoon Jeong1(1. Samsung Electronics Corp., Ltd.)
[Session_9-05]Modeling of Soft Errors in CFET SRAM Using Machine Learning-Assisted Circuit Simulation
*Vanness Filbert Cierra1, Yoshinari Kamakura1(1. Osaka Inst. Tech.)
[Session_9-06]Low-Temperature Behavior in Silicon Nanowire n-FETs Studied by Atomistic NEGF
*Sanam Moslemi-Tabrizi2, Peter Schvan2, Philippe Blaise1, Udita Kapoor1, Daniel Lemus3, Tillmann Kubis3(1. Silvaco Inc., 2. Ciena Inc., 3. Purdue Univ.)
[Session_10-01]Multi-Scale Statistical Modeling of Random Telegraph Noise in Sub-Micrometer CIS
*Jae Ho Kim1, Sungchul Kim1, Yonghee Park1, Jonhyun Go1, Jae Hoon Jung1(1. Samsung Electronics)
[Session_10-02]Antisite Disorder in the Native Oxide Insulator β-Bi2SeO5: A First-Principles Study
*Mina Bahrami Bahrami1, Mohammad Rasool Davoudi1, Dominic Waldhoer1, Christoph Wilhelmer1, Pedram Khakbaz1, Theresia Knobloch1, Michael Waltl1, Tibor Grasser1(1. Institute for Microelectronics)
[Session_10-03]A Unified Physical Model for Bias Temperature Instability in OSFETs
*Yongjia Wang1, Haotong Zhu1, Jinghan Xu1, Ligong Zhang1, Jinfeng Kang1, Xiaoyan Liu1(1. Peking Univ.)
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