Session Details
[10a-N302-1~11]13.5 Semiconductor devices/ Interconnect/ Integration technologies
Wed. Sep 10, 2025 9:00 AM - 12:00 PM JST
Wed. Sep 10, 2025 12:00 AM - 3:00 AM UTC
Wed. Sep 10, 2025 12:00 AM - 3:00 AM UTC
N302 (Lecture Hall North)
[10a-N302-1]Nanoampere Parallel Single-Electron Pumping in Silicon with Split-Source Control
〇Gento Yamahata1, Takase Shimizu1, Katsuhiko Nishiguchi1, Akira Fujiwara1 (1.NTT BRL)
[10a-N302-2]Effects of valley splitting on resonant-tunneling readout of spin qubits
〇Tetsufumi Tanamoto1, Keiji Ono2 (1.Teikyo Univ., 2.Riken)
[10a-N302-3]RF Reflectometry of Semiconductor Quantum Dots with Tunnel Diode Oscillator
〇Yuto Arakawa1, Ivan Grytsenko2, Oleksiy Rybalko2,3, Raisei Mizokuchi1, Erika Kawakami2, Tetsuo Kodera1 (1.Science Tokyo, 2.RIKEN, 3.B. Verkin Institute, NASU)
[10a-N302-4]3D Stacked Silicon Quantum Dots Utilizing Potential Barriers Formed by Barrier Gates
〇(D)Junoh Kim1, Daiki Futagi1, Tomoko Mizutani1, Takuya Saraya1, Hiroshi Oka2, Takahiro Mori2, Masaharu Kobayashi1,3, Toshiro Hiramoto1 (1.IIS, Univ. of Tokyo, 2.AIST, 3.d.lab Univ. of Tokyo)
[10a-N302-5]Experimental demonstration of Vertically Stacked Two-Layer Silicon Quantum Dots
〇(DC)Daiki Futagi1, Jun-Oh Kim1, Tomoko Mizutani1, Takuya Saraya1, Hiroshi Oka2, Takahiro Mori2, Masaharu Kobayashi1,3, Toshiro Hiramoto1 (1.IIS, UTokyo., 2.AIST, Japan., 3.d.lab, UTokyo.)
[10a-N302-6]Application of VPG-VBG Mapping to Analyze Device Characteristics of Silicon Fin-Type Quantum Dots
〇Yusuke Chiashi1, Kimihiko Kato1, Yoshihisa Iba1, Hiroshi Oka1, Shota Iizuka1, Hidehiro Asai1, Minoru Ogura1, Takumi Inaba1, Takahiro Mori1 (1.AIST)
[10a-N302-7]Implementation of cryogenic switching circuits for rapid evaluation of silicon qubit devices
〇Takeshi Fukuda1, Tatsuya Matsuda1, Ryutaro Matsuoka1, Itaru Yanagi2, Toshiyuki Mine2, Ryuta Tsuchiya2, Digh Hisamoto2, Hiroyuki Mizuno2, Raisei Mizokuchi1, Jun Yoneda1,3, Tetsuo Kodera1 (1.Science Tokyo, 2.R&D Group, Hitachi, Ltd., 3.UTokyo)
[10a-N302-8]Direct observation of electron capture processes in amphoteric defect states achieved by charge pumping in individual defects at MOS interface (17) -Definition of single defect level-
〇Toshiaki Tsuchiya1, Masahiro Hori1, Yukinori Ono1 (1.Shizuoka Univ.)
[10a-N302-9]Cryogenic conductance modeling of highly doped Si for advanced CMOS applications
〇(D)Keito Yoshinaga1, Ryo Toyoshima1, Munehiro Tada2, Ken Uchida1 (1.Univ. Tokyo, 2.Keio Univ.)
[10a-N302-10]Analysis of Subthreshold Current Variability in Bulk MOSFETs at Cryogenic Temperatures
〇Tomoko Mizutani1, Kiyoshi Takeuchi1, Takuya Saraya1, Hiroshi Oka2, Takahiro Mori2, Masaharu Kobayashi1, Toshiro Hiramoto1 (1.Univ. of Tokyo,, 2.AIST)
[10a-N302-11]Statistical Distributions of Subthreshold Current Variability in Bulk MOSFETs at Cryogenic Temperatures
〇Tomoko Mizutani1, Kiyoshi Takeuchi1, Takuya Saraya1, Hiroshi Oka2, Takahiro Mori2, Masaharu Kobayashi1, Toshiro Hiramoto1 (1.Univ. of Tokyo,, 2.AIST)