Session Details
[Mo-P]Poster Session
Mon. Sep 28, 2026 1:00 PM - 3:00 PM JST
Mon. Sep 28, 2026 4:00 AM - 6:00 AM UTC
Mon. Sep 28, 2026 4:00 AM - 6:00 AM UTC
Poster-B (4th Floor, G401+G402)
[Mo-P-37]Impact of Process Simulation and Analytical Doping Profile Simulation for 6.5 kV 4H-SiC JBS Diodes
*Xiangzhen Li1, Yumeng Cai1, Xiaoguang Wei2, Zhibin Zhao1,2, Guang Zeng3, Feng Yu3, Arne Renz4, Kyrylo Melnyk4, Zhaoxue Yuan4, Marina Antoniou4 (1. North China Electric Power University (China), 2. Huairou Laboratory (China), 3. Greenel Semiconductor Co. (China), 4. University of Warwick (UK))
[Mo-P-38]Process Integration Strategies for High-Yield Manufacturing of Large-Area 6.5-kV SiC MOSFETs
*Youngsang Kim1, Chris Wu1, Benjamin Wang1, Justin Lynch2, Alecsander N Imhof3, Nadeemullah A Mahadik3, Rachael L Myers-Ward3, Seung-Yup Jang2, Adam J Morgan2, Woongje Sung2, Michael Owen1, Anant A Agarwal2 (1. Defense Microelectronics Activity (DMEA) (USA), 2. NoMIS Power (USA), 3. U.S. Naval Research Lab. (USA))
[Mo-P-39]TCAD-Based Optimization and Experimental Validation of a 3.3kV 4H-SiC MOSFET Utilizing an Epitaxially Grown Current-Spreading Layer
*Stephen A Mancini1, Seung Yup Jang1,3, Andrew Binder2, Richard Floyd2, Robert Kaplar2, Jack Flicker2, Stan Attcity2, Adam Morgan3, Woongje Sung1 (1. Univ. at Albany (USA), 2. Sandia National Labs (USA), 3. NoMIS Power Corp. (USA))
[Mo-P-40]Dual Densification Routes for Additively Manufactured Silicon Carbide Components Used in Semiconductor Processing Equipment
*Youngsuk Jung1, Ji-Won Oh, Shinhu Cho (1. MADDE Inc. (Korea))
[Mo-P-41]Thermal History Driven PEB Behavior on Si and 4H SiC Substrates in a KrF Lithography Process Using a Production Coater Developer Track
*Yuji Tanaka1, Naser Belmiloud1, Pierre Sixt2, Raphaël Feougier2, Béatrice Hemard2 (1. SCREEN SPE Germany GmbH (Germany), 2. Univ. Grenoble Alpes, CEA, Leti (France))
[Mo-P-42]Improving Surface Roughness and Internal Stress by UV Nanosecond Laser Treatment for Laser-Structured 4H-SiC with Micro Pin-Fin Arrays
*Hsiang-En Weng1, Ping-Yu Lin1, Chiao-Yang Cheng1, Di-Hua Huang2, Yi-Chang Wu3, Zi-Hao Wang1, Yang-Kuin Su1 (1. National Cheng Kung Univ. (Taiwan), 2. JUMBO LASER CO Ltd. (Taiwan), 3. GeChi Compound Semiconductor Crop Ltd. (Taiwan))
[Mo-P-43]Evaluation of Processing Stability and Kerf Width Reduction in BPD-free Dicing of SiC Wafer Using Water Jet Guided Laser
*Hyuk Kim1, Shunya Hirano1, Satoru Takahashi2, Shuzo Masui2, Noboru Ohtani3, Kozo Abe3 (1. MAKINO MILLING MACHINE CO., LTD. (Japan), 2. The University of Tokyo (Japan), 3. Kwansei Gakuin University (Japan))
[Mo-P-44]Characterization of 6-inch 4H-SiC Non-Epitaxial Engineered
Substrates
*Hitesh Jayaprakash1,2,3, Alexander Schmid4, Thomas Behm4, Constantin Csato2, Florian Krippendorf2, Michael Rueb2,3 (1. Freidrich Alexander Universität, Erlangen (Germany), 2. mi2-factory GmbH (Germany), 3. Ernst-Abbe-Hochschule, Jena (Germany), 4. Technische Universität Bergakademie Freiberg (Germany))
[Mo-P-45]Mitigation of bipolar degradation in 4H-SiC power devices using SmartSiCTM engineered substrates
*Endong Zhang1, Alexis Drouin2, Frederic Allibert2, Marcin Zielinski2, Shunta Harada3 (1. Nagoya Inst. of Tech. (Japan), 2. SOITEC (France), 3. Nagoya Univ. (Japan))
[Mo-P-46]Trade-Off Between Forward Conduction and Reverse Leakage in O2 Annealed Ga2O3/SiC Schottky Barrier Diodes
*In-Sung Ku1, Hyeon-Do Kang1, Minseok Kim1, Jin-Woo Choi1, Sabeen Hwang1, Tae-Yeong Yoon1, Sang-Mo Koo1 (1. Kwangwoon University (Korea))
[Mo-P-47]Sequential surface engineering using UV/O3 and O2 plasma for defect control in Ga2O3/4H-SiC Heterojunctions
*juhyeon Son1 (1. Kwangwoon University (Korea))
[Mo-P-48]Effects of N2 Post-Annealing on the Electrical Characteristics of p-Cu2O/β-Ga2O3 Heterojunction Diodes
*Tae-Yeong Yoon1, Jin-Woo Choi1, Minseok Kim1, Sabeen Hwang1, Chang-Jun Park1, JuHyeon Son1, Sang-Mo Koo1 (1. Kwangwoon Univ. (Korea))
[Mo-P-49]Structural Origin of Inversion Layer Formation via Stacking-Fault-Mediated Hole Transport in 3C/4H-SiC MOS Structures
*Kota Gejo1, Tetsuo Hatakeyama1, Hiroyuki Nagasawa2 (1. Univ. of Toyama Pref (Japan), 2. Cusic Inc (Japan))
[Mo-P-50]Analytical Method for Parameter Extraction From Hall Measurement Data in Aluminum Implanted SiC Test Structures
*Edmund K Banghart1, Daniel J Lichtenwalner1, Hemant Dixit1, Sei-Hyung Ryu1 (1. Wolfspeed (USA))
[Mo-P-51]Dual-Path Current in Accumulation-Type SiC MOSFETs
*AMJED ALI1,2, Daniel Haasmann, Philip Tanner, Jordan Nicholls, Sima Dimitrijev (1. School of Engineering and Built Environment, Griffith University, Nathan, Qld (Australia), 2. Queensland Quantum and Advanced Technologies Research Institute, Griffith University, Nathan, Qld (Australia))
[Mo-P-52]Measurement of Temperature-Dependent Large-Signal Hysteresis in Output Capacitance of SiC MOSFETs
*Taiki Nishioka1, Hajime Takayama1, Kazutaka Kanegae1, Hiroyuki Nishinaka1, Michihiro Shintani1 (1. Kyoto Inst. of Tech. (Japan))
[Mo-P-53]Curve Tracer Approach for Accurate Characterization of Output Characteristics of SiC MOSFETs in 1st and 3rd Quadrant
*Maximilian Paul Goller1, Mohamed Alaluss1, Madhu Lakshman Mysore1, Gengqi Li1, Dezhi Yang1, Josef Lutz1, Thomas Basler1 (1. Chemnitz University of Technology (Germany))
[Mo-P-54]Impact of P+ Body Layout on Capacitance and Third Quadrant Characteristics of Tri-Gate SiC MOSFETs
Pei-Chi Liao1, *Kung-Yen Lee1,2, Pei-Chun Liao1, Ruei-Ci Wu2, Yu-Ying Li1, Yung-Mei Lin1 (1. National Taiwan University (Taiwan), 2. SiCEV Electronics Co., Hsinchu (Taiwan))
[Mo-P-55]Variation of Dynamic Characteristics in SiC MOSFETs induced by Edge Termination Topology
*PEI-CHUN LIAO1, KUNG-YEN LEE1,2, YAN-YU WEN1, PEI-CHI LIAO1, TIEN-CHIN SHIH2, RUEI-CI WU3 (1. Graduate School of Advanced Technology, National Taiwan Univ. (Taiwan), 2. Department of Engineering Science and Ocean Engineering, National Taiwan Univ. (Taiwan), 3. SiCEV Electronics Co., Ltd., Taiwan (Taiwan))
[Mo-P-56]Dynamic C-V Characterization of Commercial SiC Power MOSFETs
*Tibet Alpay1, Michel Nagel1, Ivana Kovacevic-Badstuebner1, Ulrike Grossner1 (1. APS - ETH Zurich (Switzerland))
[Mo-P-57]Miller Capacitance Characterization of SiC Power MOSFETs Beyond Datasheets
*Michel Nagel1, Ivana Kovacevic-Badstuebner1, Ulrike Grossner1 (1. APS - ETH Zurich (Switzerland))
[Mo-P-58]3D vs. 2D TCAD: The Right Choice for Simulating 4H-SiC MOSFETs?
*Hemant Dixit1, Jae Park1, Jeff Joohyung Kim1, Sei-Hyung Ryu1 (1. Wolfspeed (USA))
[Mo-P-59]Physics-based Compact Model of SiC Power MOSFET for Process Corner Analysis
*Arman Ur Rashid1, Jeff Joohyung Kim1, Edmund Banghart1, Sei-Hyung Ryu1 (1. Wolfspeed, Inc. (USA))
[Mo-P-60]Robust and Universal SPICE Model Structure for Variable Capacitance with Negative-Feedback Configuration
*Yuichiro Nanen1 (1. ROHM co. Ltd. (Japan))
[Mo-P-61]A Modified Coupled Charge-driven Reverse Recovery SPICE Model for Describing the Dynamic Behavior of SiC MOSFETs’ Intrinsic Body Diode
*Ting-Fu Chang1, Fu-Jen Hsu1,2, Hsiang-Ting Hung1, Chung-Ju Yu1, Cheng-Tyng Yen1, Chih-Fang Huang2 (1. Fast SiC Semiconductor Inc. (Taiwan), 2. National Tsing Hua University (Taiwan))