Session Details
[16p-B1-1~14]13.4 Si processing /Si based thin film / MEMS / Equipment technology
Mon. Sep 16, 2024 1:00 PM - 5:00 PM JST
Mon. Sep 16, 2024 4:00 AM - 8:00 AM UTC
Mon. Sep 16, 2024 4:00 AM - 8:00 AM UTC
B1 (Exhibition Hall B)
Wenchang Yeh(Shimane Univ.), Tatsuya Okada(Univ. of the Ryukyus), Naoya Okada(AIST)
[16p-B1-1]Periodic Dimple Lines Observed in the (100) Grain-Boundary Free Si Thin Films Obtained by the CW Laser Crystallization
〇Nobuo Sasaki1,2, Satoshi Takayama2, Yukiharu Uraoka2 (1.Sasaki Consulting, 2.NAIST)
[16p-B1-2]DG poly-Ge TFTs fabricated on glass substrates by using gate last process
〇(M2)Daiki Goshima1, Akito Kurihara1, Sho Suzuki1, Akito Hara1 (1.Tohoku Gakuin Univ)
[16p-B1-3]4T vertical poly-Si TFT for pH sensor on glass substrates
〇Kosei Suzuki1, Tetsuo Tabei2, Akito Hara1 (1.Tohoku Gakuin Univ., 2.Hiroshima Univ. RISE)
[16p-B1-4]Crystallization of a-Si Films Deposited by CVD using Blue Direct Diode Laser
〇Tatsuya Okada1, Takashi Noguchi1, Mitsuoki Hishida2, Kentaro Miyano2, Naohiko Kobata2, Masaki Nobuoka2 (1.Univ. Ryukyus, 2.Panasonic Connect)
[16p-B1-5]Performance Improvement of n-channel TFT on Solid-Phase Crystallized poly-Ge by Channel Width Shrinking
〇linyu huang1, atsuki morimoto1, kota igura2, takamitsu ishiyama2, kaoru toko2, dong wang1, keisuke yamamoto1 (1.Kyushu Univ., 2.Univ. of Tsukuba)
[16p-B1-6]Formation of Polycrystalline Ge CMOS Inverter on Glass Substrate
〇Atsuki Morimoto1, Linyu Huang1, Kota Igura2, Takamitsu Ishiyama2, Kaoru Toko2, Dong Wang1, Keisuke Yamamoto1 (1.Kyushu Univ., 2.Univ. of Tsukuba)
[16p-B1-7]µCLS (001) Single Crystal MOSFET Fabricated by All Sputter Processes
〇(M1)Ryota Nosu1, Wenchang Yeh1 (1.Shimane Univ.)
[16p-B1-8]Spectroscopic ellipsometry characterization of SiGe/Si super lattice toward building of 300 mm GAAFET pilot-line
〇Naoto Kumagai1, Akio Fukushima1, Chia-Tsong Chen1, Kazuya Uejima1, Toshifumi Irisawa1, Yoshihiro Hayashi1 (1.AIST)
[16p-B1-9]Mechanisms Controlling the Effective Work Function of TiN/TiAlC Metal Gates for Advanced Gate-all-around CMOS
〇Kenzo Manabe1, Kazuya Uejima1, Hiroyuki Ota1, Yukinori Morita1, Toshifumi Irisawa1, Yoshihiro Hayashi1 (1.SFRC, AIST)
[16p-B1-10]Study on Selective Dry Etching of Epitaxially Grown Si0.7Ge0.3 and Si using H2 Diluted CF4
〇(M1)Kotaro Ozaki1, Noriharu Takada2, Takayoshi Tsutsumi2, Kenji Ishikawa2, Yuji Yamamoto3, Wei-Chen Wen3, Katsunori Makihara1 (1.Nagoya Univ., 2.Nagoya Univ. cLPS, 3.IHP)
[16p-B1-11]Ni-silicide Formation and Crystalline Phase Control
〇Shun Tanida1, Noriyuki Taoka2, Katsunori Makihara1 (1.Nagoya Univ., 2.Aichi Inst. Tech.)
[16p-B1-12]Evaluation of Interstitial Si Diffusion generated by Si Trench Processing using Low Temperature Photoluminescence Spectroscopy
〇Ryota Fujimori1, Yuta Ito1, Ryo Yokogawa1,2, Atsushi Ogura1,2, Kazuto Kawakatsu3, Nobuyuki Kuboi3, Koichiro Saga3, Yuto Iwamoto3 (1.Meiji Univ., 2.MREL, 3.Sony Semiconductor Solutions)
[16p-B1-13]Effects of unifying temperature over a substrate during Freeze Cleaning Method
〇Satoshi Nakamura1, Kensuke Demura1, Masashi Yamage1, Kei Hattori2 (1.Shibaura Mechatronics Corp., 2.Nagoya Univ. Center for Low-Temperature Plasma Sciences)
[16p-B1-14]Evaluation of anomaly detection using cluster analysis for semiconductor manufacturing equipment
〇Yuki Shiga1, Toshiya Hirai1,2, Manabu Kano2 (1.KOKUSAI ELECTRIC, 2.Kyoto Univ.)