Session Details
[We-P]Poster Session
Wed. Sep 30, 2026 4:00 PM - 6:00 PM JST
Wed. Sep 30, 2026 7:00 AM - 9:00 AM UTC
Wed. Sep 30, 2026 7:00 AM - 9:00 AM UTC
Poster-A (1st Floor)
[We-IP]Gate-Oxide Protection for Enhanced Single-Event Robustness in SiC Power MOSFETs
*Heng WANG1,2, Yun XIA1, LyuZhang PENG3, ChangWei Zheng1, SiRui FENG1, XinPeng LIN1, Pengwei ZHOU2, YingChen YANG2, Gang CHEN1, YuXi WAN1, Gang Lyu3, Kevin Jing CHEN2 (1. Shenzhen Pinghu Lab. (China), 2. The Hong Kong Univ. of Sci. and Tech. (Hong Kong), 3. Beihang Univ. (China))
[We-P-01]Demonstration of 4H-SiC JBSFETs with Split-Gate Architecture for Improved High Voltage Performance
*Anas Malek Moumani1, Justin Lynch1, Stephen Mancini1, Woongje Sung1, Miguel Hinojosa2, Ronald Green2, Aivars Lelis2 (1. Univ. at Albany, SUNY (USA), 2. US Army Res. Lab (USA))
[We-P-02]Suppression of Forward Bias Degradation in 3.3kV DMOSFET Fabricated on 4H-SiC Bonded Substrates
*Seiji Ishikawa1, Yuta Higashi2, Motoki Kobayashi3, Mitsuo Okamoto1, Kazutoshi Kojima1, Shinsuke Harada1 (1. Advanced Power Electronics Research Center, National Institute of Advanced Industrial Science and Tech. (Japan), 2. PHENITEC SEMICONDUCTOR Corp. (Japan), 3. Sumitomo Metal Mining Co., Ltd. (Japan))
[We-P-03]Experimental Demonstration of Improved On-State Performance in 3.3 kV 3D Quasi-Planar Trench SiC MOSFET
*Mansha Kansal1, Munaf Rahimo2, Kyrylo Melnyk3, Giuseppe Capasso1, Alessandro Borghese1, Michele Riccio1, Arne Benjamin Renz3, Giovanni Breglio1, Neophytos Lophitis4, Andrea Irace1, Marina Antoniou3, Iulian Nistor2, Luca Maresca1 (1. University of Naples Federico II (Italy), 2. mQsemi AG (Switzerland), 3. University of Warwick, Warwick, UK (UK), 4. Cyprus University of Technology (Cyprus))
[We-P-04]Demonstration of a 3.3 kV-rating VDMOSFET with Ultra-low Specific on-Resistance
*Han-Wei Chen1, Yun-Ting Huang1, I-Chen Tsai1, Yu-Xin Wen1, Bing-Yue Tsui1 (1. Univ. of National Yang Ming Chiao Tung (Taiwan))
[We-P-05]3.3 kV-Class 4H-SiC TMBS Diodes and TMBS-Embedded UMOSFETs
*Jun-Kai Huang1, Jia-Wei Hu1, Te-Jui Lee1, Chih-Chun Ouyang1, Guan-Min Kang1, Chih-Fang Huang1 (1. National Tsing Hua Univ. (Taiwan))
[We-P-06]Characterization and Modeling of Third Quadrant Operation in High Voltage 4H-SiC Superjunction DMOSFET
Zhaowen He1, Collin Hitchcock2, Stacey Kennerly2, Reza Ghandi2, *Tat-sing Paul Chow1 (1. Rensselaer Polytechnic Institute (USA), 2. GE Aerospace (USA))
[We-P-07]Multi-Epitaxy with Channeling Implantation and Deep Trench Design for 3.3 kV Semi-Superjunction MOSFET
*Kyrylo Melnyk1, Arne Benjamin Renz1, Mustafa Akif Yildirim1, Vishal Ajit Shah1, Peter Michael Gammon1, Marina Antoniou1 (1. University of Warwick (UK))
[We-P-08]Design Considerations for 3.3 kV and 6.5 kV 4H-SiC MOSFETs
*Justin Lynch1, Seung Yup Jang1, Adam J. Morgan1, Woongje Sung1, Youngsang Kim2, Michael Owen2, Nadeemullah A. Mahadik3, Alecsander N. Imhof3, Rachel L. Myers-Ward3 (1. NoMIS Power Corporation (USA), 2. Defense Microelectronics Activity (USA), 3. U.S. Naval Research Laboratory (USA))
[We-P-09]Robust 4H-SiC 6.5 kV Edge Termination Based on Floating Field Rings and JTE Termination Design and Optimization
*Zhaoxue Yuan1, Arne Renz1, Nikolaos Iosifidis1, Xinghua Wang2, Xiao Gong2,3, Umesh Chand2, Abhishek Mishra2, Xiaolin Wang2,3, Marina Antoniou1, Peter Gammon1 (1. Univ. of Warwick (UK), 2. Institute of Microelectronics, Agency for Science, Technology, and Research (A*STAR) (Singapore), 3. National University of Singapore (Singapore))
[We-P-10]Comparison of On-State and Switching Performance of High-Voltage 4H-SiC n-Channel IGBTs and DMOSFETs
*Thomas Gonzaga1, Dallas Morisette1, James Cooper2 (1. Purdue Univ. (USA), 2. Sonrisa Res. (USA))
[We-P-11]Wafer-Level Testing of SiC Power Devices > 10 kV: Methods, Limitaions and Challenges
*Marcel Dinse1, Nadja Klipfel2, Nazareno Donato3, Jan-Hendrik Peters1, Giovanni Alfieri2, Marco Pocaterra2, Sami Bolat2, Nando Kaminski1 (1. Univ. of Bremen (Germany), 2. Hitachi Energy Ltd. (Switzerland), 3. Univ. of Cambridge (UK))
[We-P-12]OBIC Measurements On 4H-SiC Thyristors Protected by Etched Junction Termination Extension
*Rabei Barhoumi1, Luong-Viet Phung1, Camille Sonneville1, Sigo Scharnholz2, Milan Zuvic2, Ralf Hassdorf2, Dominique Planson1 (1. Univ. of Lyon (France), 2. French-German Research Institute of Saint-Louis (ISL) (France))
[We-P-13]Electrical Response and SEB of Trench-MOSFETs after Heavy-Ion
Irradation
*Axel Erlebach1, Helton Goncalves de Medeiros1, Natalija Für1, Manuel Belanche1, Ulrike Grossner1 (1. APS - ETH Zurich (Switzerland))
[We-P-14]3D Investigation of Heavy Ion Induced Single Event Effects in a Double RESURF SiC Power Device
*Zhaoxue Yuan1, Bailing Zhou1, Peter Gammon1, Marina Antoniou1 (1. Univ. of Warwick (UK))
[We-P-15]Influence of Buffer Profile on the Single Event Immunity of 4H-SiC Epitaxial Stacks under Heavy-Ion Irradiation
*Gabriel Scott Parkinson1, Peter Gammon2, Niamh Arnold2, Virendra Kotagama2, Rishad Ahmed1, Paul Evans1, Neophytos Lophitis3 (1. Univ. of Nottingham (UK), 2. Univ. of Warwick (UK), 3. Cyprus Univ. of Tech. (Cyprus))
[We-P-16]Single Event Transient Suppression in 4H-SiC MOSFETs on V-doped Semi-Insulating Substrates
*Taisei Ozaki1, Takahiro Makino2, Kazutoshi Kojima3, Takeshi Ohshima2, Shin-Ichiro Kuroki1 (1. Hiroshima Univ. (Japan), 2. QST (Japan), 3. AIST (Japan))
[We-P-17]Leakage current instability of Gamma-ray-irradiated SiC junction field effect transistors
*Akinori Takeyama1, Takahiro Makino1, Yasunori Tanaka2, Shin-Ichiro Kuroki3, Takeshi Ohshima1 (1. National Institutes for Quantum Science and Technology (QST) (Japan), 2. National Institute of Advanced Industrial Science and Technology (AIST) (Japan), 3. Research Institute for Semiconductor Engineering, Hiroshima University (Japan))
[We-P-18]Effect of gamma-ray irradiation on the I-V characteristics of level shifting diodes in SiC JFET analog circuits
*Masayuki Yamamoto1,2, Ryuya Hirose1,2, Daisuke Watanabe1,2, Akinori Takeyama3, Hitoshi Umezawa1, Takahide Sato2, Takahiro Makino3, Takeshi Ohshima3, Shin-ichiro Kuroki4 (1. National Institute of Advanced Industrial Science and Technology (AIST) (Japan), 2. University of Yamanashi (Japan), 3. QST (Japan), 4. Hiroshima University (Japan))
[We-P-19]A Monolithically Integrated SiC JFET Differential Amplifier: From MPW Fabrication and Low-Voltage Verification to Common-Mode Rejection Optimization
*Haizhao Zhi1, Sirui Feng1, Ronxin Du1, Ling Li1, Xinpeng Lin1, Mengqi Fan1, Xinyue Dai1, Xiaoping Wang1, Yuxi Wan1 (1. Shenzhen Pinghu Laboratory (China))
[We-P-20]Thermal Degradation Behavior in a Double-Sided Cooling SiC Power Module Revealed by Structure Function Analysis
*Jonghyeon Ryu1, Gyuhyeok Kang1, Yeonghyeon Kim1, Jeongwoo Choi2, Junho Lee2, Ogyun Seok1 (1. Pusan National University (Korea), 2. JMJ Korea (Korea))
[We-P-21]Comparative Study of Gate Oxide Screening With Adjustment Pulse Technique using Commercial and In-House 4H-SiC MOSFETs
*Monikuntala Bhattacharya1, Michael Jin2, Marvin H White2, Atsushi Shimbori3, Anant K Agarwal2 (1. L&T Semiconductor Technologies (India), 2. The Ohio State University (USA), 3. Ford Motor Company (USA))
[We-P-22]Achieving Extrinsic-Free Gate Oxide Reliability in 1200 V SiC MOSFETs: A Large-Scale Statistical Study Validating the Thermo-Cheminal E-Model at 175 ℃
*DAHUI YOO1, Chang-Heon Yang1, Wonchul Baek2, Soochang Kang2, Lorenzo Marchesi3, Alessandro Polpetta3, In-Hwan Ji2, Derek Lee2 (1. SK-powertech Inc. (Korea), 2. SK-Keyfoundry Inc. (Korea), 3. EDA Indus. (Italy))
[We-P-23]Gate Oxide Integrity and Lifetime Prediction of 1.2 kV SiC MOSFETs under Step-Wise Increased Gate Bias
*Roman Boldyrjew-Mast1, Thomas Basler1 (1. Chemnitz Univ. of Technology (Germany))
[We-P-24]Experimental Identification of Continuous Field-Driven
Degradation Mechanism Transition in SiC MOSFETs under DC
TDDB Stress
*Sota Sugimori1, Shuhei Nakata1 (1. Kanazawa Institute of Technology (Japan))
[We-P-25]Investigation of Electro-Thermal TDDB Degradation in 1.2 kV SiC MOSFETs
*Ahmed A. Ibrahim1, Mohammad Monfared1, Saeed Jahdi2, Mohamed Amer Karout3, Craig Fisher1, Mike Jennings1 (1. Swansea Univ. (UK), 2. Univ. of Bristol (UK), 3. Univ. of Warwick (UK))
[We-P-26]A New Charge-to-breakdown-based Lifetime Prediction Model for Thermally Grown Gate Oxides in SiC Power MOSFETs
*Jiashu Qian1, Hengyu Yu1, Limeng Shi1, Michael Jin1, Monikuntala Bhattacharya1, Atsushi Shimbori2, Marvin H. White1, Anant K. Agarwal1 (1. The Ohio State University (USA), 2. Ford Auto Co. (USA))
[We-P-27]Impact of Gate-Voltage Rise Time on AC-TDDB Lifetime Statistics in SiC MOSFETs
*Kosei Yokoyama1, SHUHEI NAKATA1 (1. Kanazawa Institute of Technology (Japan))