[A-1-1]Control of Interface Properties of High-k/Ge with GeO2 Interface Layer (Invited)
K. Kita1、T. Nishimura1、K. Nagashio1、A. Toriumi1(1.Univ. of Tokyo, Japan)
2008 International Conference on Solid State Devices and Materials
2008年9月23日〜9月26日Tsukuba International Congress Center (EPOCHAL TSUKUBA), Ibaraki, Japan
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2008 International Conference on Solid State Devices and Materials
2008年9月23日〜9月26日Tsukuba International Congress Center (EPOCHAL TSUKUBA), Ibaraki, Japan
当該イベント内で検索します。
検索する検索結果(587)
[A-1-2]High-k Gated Germanium Metal-Oxide-Semiconductor Capacitors with GeO2 Surface Passivation and Fluorine Incorporation
R. Xie1,2、W. He1、M. Yu2、C. Zhu1(1.National Univ. of Singapore、2.Inst. of Microelectronics, Singapore)
[A-1-3]Improvement of Interface Properties of GeO2/Ge MOS Structures Fabricated by Thermal Oxidation
T. Sasada1、H. Matsubara1、M. Takenaka1、S. Takagi1(1.Univ. of Tokyo, Japan)
[A-1-4]Amorphous High-k LaLuO3 Dielectric Film for Ge MIS Gate Stack
T. Tabata1、K. Kita1、A. Toriumi1(1.Univ. of Tokyo, Japan)
[A-1-5]Reaction Kinetics Control on Thermal Oxidation Process of Ge in High Pressure Oxygen
C. H. Lee1、T. Nishimura1、K. Nagashio1、K. Kita1、A. Toriumi1(1.Univ. of Tokyo, Japan)
[A-2-1]Performance and Reliability of High-k/Metal Gate Stacks: Interfacial Layer Defects (Invited)
G. Bersuker1(1.SEMATECH, USA)
[A-2-2]Impact of the Activation Annealing Temperature on the Performance, NBTI and TDDB Lifetime of High-k/Metal Gate Stack pMOSFETs
M. Sato1、T. Aoyama1、Y. Nara1、Y. Ohji1(1.Selete, Japan)
[A-2-3]Mechanisms of Oxygen and Hydrogen Passivation using High Pressure Post-annealing Processes to Enhance the Performance of MOSFETs with Metal Gate/High-k Dielectric
C. Y. Kang1、C. S. Park1、H. K. Park1、S. C. Song1、R. Choi1、B. H. Park2、B. Woo2、K. T. Lee3、J. Lee4、H. Hwang4、G. Bersuker1、B. H. Lee1、H. H. Tseng1、R. Jammy5(1.SEMATECH、2.Poongsan Microtech, USA、3.POSTECH、4.GIST, Korea、5.IBM Assignee, USA)
[A-2-4]Vt Variation Suppressed Al2O3-Capped HfO2 Gate Dielectrics for Low Vt pMISFETs with High-k/Metal Gate Stacks
T. Morooka1、T. Matsuki1、N. Mise1、S. Kamiyama1、T. Nabatame1、T. Eimori1、Y. Nara1、Y. Ohji1(1.Selete, Japan)
[A-2-5]Generation of a New Interface-State Associated with Ultra-Thin Gate Dielectrics/Silicon under Electric Stress
H. Mori1、H. Matsuyama1、S. Watanabe2(1.Fujitsu Microelectronics Ltd.、2.Fujitsu Labs. Ltd., Japan)
[A-3-1]Dopant and Potential Profiling with Atomic Resolution by Scanning Tunneling Microscopy (Invited)
T. Kanayama1、M. Nishizawa1、L. Bolotov1(1.MIRAI-AIST, Japan)
[A-3-2]1-nm Spatial Resolution in Carrier Mapping of Ultra-Shallow Junctions by Scanning Spreading Resistance Microscopy
L. Zhang1、H. Tanimoto1、K. Adachi1、N. Yasutake1、A. Nishiyama1(1.Toshiba Corp., Japan)
[A-3-3]Carrier Density Mapping of Small n-MOSFET Devices by Vacuum-gap Modulation Scanning Tunneling Spectroscopy
L. Bolotov1、M. Nishizawa1、T. Kanayama1(1.MIRAI-AIST, Japan)
[A-3-4]Trap Generation in Sc2O3/La2O3 High-κ Gate Stack by Nanoscale Electrical Stress
Y. C. Ong1、D. S. Ang1、S. J. O'Shea2、K. L. Pey1、C. H. Tung3、T. Kawanago4、K. Kakushima4、H. Iwai4(1.Nanyang Tech. Univ.、2.Inst. of Materials Res. and Eng.、3.Inst. of Microelectronics, Singapore、4.Tokyo Tech., Japan)
[A-5-1]Defect Profiling and the Role of Nitrogen in Lanthanum Oxide-capped High-κ Dielectrics for nMOS Applications
B. J. O'Sullivan1、R. Mitsuhashi2、H. Okawa2、N. Sengoku2、T. Schram1、G. Groeseneken1,3、S. Biesemans1、T. Nakabayashi2、A. Ikeda2、M. Niwa2(1.IMEC, Belgium、2.Matsushita Electric Co., Ltd., Japan、3.Katholieke Univ., Belgium)
[A-5-2]Chemical Bonding-Induced Dipole at the HfO2/Si Interface
N. Miyata1,2、Y. Abe1,2、T. Yasuda1(1.AIST、2.Musashi Inst. of Tech., Japan)
[A-5-3]Photoemission Study of Chemical Bonding Features and Electronic States of Ultrathin HfTixOy/Pt System
A. Ohta1、H. Murakami1、S. Higashi1、S. Miyazaki1、M. Tanioku2、M. Horikawa2、A. Ogishima2(1.Hiroshima Univ.、2.Elpida Memory Inc., Japan)
[A-6-1]Self-limiting Growth Behavior of Epitaxial NiSi2 and its Impact on Controlled Silicidation of Metal Source/Drain in Silicon Nanowire MOSFETs
S. Migita1、Y. Morita1、N. Taoka1、W. Mizubayashi1、H. Ota1(1.AIST, Japan)
[A-6-2]Low Temperature Phosphorus Segregation at NiGe/Ge Interface by "Snowplow" Effect
T. Nishimura1、S. Sakata1、K. Nagashio1、K. Kita1、A. Toriumi1(1.Univ. of Tokyo, Japan)
[A-6-3]Formation of Low Resistive S/D-Extension using Carborane Molecular Ion Implantation for Sub-45-nm PMOSFET
S. Endo1、Y. Kawasaki1、T. Yamashita1、H. Oda1、Y. Inoue1(1.Renesas Tech. Corp., Japan)
[A-6-4]Schottky-Barrier Height Tuning of Nickel Silicide on Epitaxial Silicon-Carbon Films with High Substitutional Carbon Content
P. S. Y. Lim1、R. T. P. Lee1、A. E. J. Lim1、A. T. Y. Koh1、M. Sinha1、D. Z. Chi2、Y. C. Yeo1(1.National Univ. of Singapore、2.Inst. of Materials Res. and Eng., Singapore)
[A-7-1]Pushing Bulk Transistor with Conventional SiON Gate Oxide for Low Power Applications
G. Bidal1,3、F. Boeuf1、F. Payet1、S. Denorme1、N. Loubet1、P. Perreau2、C. Mezzomo1,3、M. Marin1、D. Fleury1,3、C. Leyris1、F. Leverd1、P. Gouraud1、C. Laviron2、R. Beneyton1、A. Torres2、B. Imbert1、D. Delille4、L. Clement1、G. Ghibaudo3、T. Skotnicki1(1.STMicroelectronics、2.CEA-LETI、3.IMEP, France、4.FEI, Netherlands)
[A-7-2]Additive Process Induced Strain (APIS) Technology for Lg = 30nm Band-Edge High-k/Metal Gate nMOSFET
M. M. Hussain1、K. Rader2、C. Smith3、C. Young1、S. Suthram4、C. Park1、M. Cruz1、P. D. Kirsch1、R. Jammy5(1.SEMATECH、2.Texas State Univ.、3.Univ. of North Texas、4.Univ. of Florida、5.IBM Assignee, USA)
[A-7-3]Vertical Scaling of Metal/High-k Gate Stacked MOSFETs for Hp45 and Beyond
T. Matsuki1、T. Watanabe1、T. Morooka1、M. Sato1、M. Kadoshima1、T. Onizawa1、T. Eimori1、M. Nakamura1、Y. Nara1、Y. Ohji1(1.Selete, Japan)
[A-7-4]Vfb Lowering Effect of TaC/Rare Earth Metal/TaC Laminated Gate Electrode Applicable to N-MISFET with HfSiON and its Physical Origins before and after High-Temperature Annealing
R. Ichihara1、M. Koyama1(1.Toshiba Corp., Japan)
[A-8-1]Low Vt Metal-Gate/High-k CMOS from Understanding the Mechanism to Innovative Solution (Invited)
A. Chin1,2、C. H. Cheng2、N. C. Su3、S. J. Wang3、C. C. Liao1,2、C. P. Chou2、H. L. Hwang1,4(1.Nano-Electronics Consortium of Taiwan、2.National Chiao Tung Univ.、3.National Cheng Kung Univ.、4.National Tsing Hua Univ., Taiwan)
[A-8-2]Improvement of Metal/High-k Device Performance by 40-Milli-Second Flash Lamp Annealing by using Flexibly-Shaped-Pulse Technology
T. Onizawa1、S. Kato1、T. Aoyama1、Y. Nara1、Y. Ohji1(1.Selete, Japan)
[A-8-3]Dual Metal Gate Technology with Metal Inserted FUSI Stack (MIFS) using Single Phase FUSI for Scaled High-k CMOSFETs
M. Kadoshima1、T. Matsuki1、T. Aminaka1、E. Kurosawa1、M. Kitajima1、T. Aoyama1、Y. Nara1、Y. Ohji1(1.Selete, Japan)
[A-8-4]Hybrid Gate Structures of NMOS : Poly-Si / PMOS : 2 Layers Ni-FUSI by using Flash Lamp Anneal (FLA) and CMP
H. Ohta1、S. Akiyama2、H. Fukutome1、K. Ookubo2、K. Kawamura2、N. Idani2、S. Satoh1(1.Fujitsu Labs. Ltd.、2.Fujitsu Microelectronics Ltd., Japan)
[A-9-1]Influence of the Light Irradiation on Galvanic Corrosion of Metal Gate
D. Watanabe1,2、H. Aoki1、J. Jong-Hyeon1、C. Kimura1、T. Sugino1(1.Osaka Univ.、2.Daikin Industries, Ltd., Japan)
[A-9-2]Millisecond Rapid Thermal Annealing of Si Wafer Induced by High Density Thermal Plasma Jet Irradiation
H. Furukawa1、S. Higashi1、T. Okada1、H. Murakami1、S. Miyazaki1(1.Hiroshima Univ., Japan)
[A-9-3]Carbon-Free Tantalum-Nitride Film from Ammonia and Extremely Diluted Pentakis-dimethylamino-Tantalum; Effect of Silicon Incorporation to nMIS-FET Metal-Gate
Y. Sugita1、T. Aoyama1、Y. Nara1(1.Selete, Japan)
[A-9-4]Metalorganic Chemical Vapor Deposition of High-Dielectric-Constant Praseodymium Oxide Films using a Liquid Cyclopentadienyl Precursor
H. Kondo1、S. Sakurai1、A. Sakai2、M. Ogawa1、S. Zaima1(1.Nagoya Univ.、2.Osaka Univ., Japan)
[A-9-5]Extended EOT Scalability of HfON/SiON Gate Stack Down to 0.57 nm with High Carrier Mobility by Post-Deposition Annealing
D. Ishikawa1、S. Kamiyama1、E. Kurosawa1、T. Aoyama1、Y. Nara1(1.Selete, Japan)
[B-1-1]III-V CMOS: Challenges and Opportunities (Invited)
J. A. del Alamo1、D. H. Kim1、N. Waldron1(1.MIT, USA)
[B-1-2]Enhancement-Mode In0.53Ga0.47As n-MOSFET with Self-aligned Gate-first Process and CVD HfAlO Gate Dielectric
J. Lin1、S. J. Lee1、H. J. Oh1、G. K. Dalapati2、D. Z. Chi2、G. Q. Lo3、D. L. Kwong3(1.National Univ. of Singapore、2.Inst. of Materials Res. and Eng.、3.Inst. of Microelectronics, Singapore)
[B-1-3]High Mobility sub-60nm Gate Length Germanium-On-Insulator Channel pMOSFETs with Metal Source/Drain and TaN MIPS Gate
K. Ikeda1、Y. Yamashita1、M. Harada1、T. Yamamoto1、S. Nakaharai1、N. Hirashita1、Y. Moriyama1、T. Tezuka1、N. Taoka2、I. Watanabe3、N. Hirose3、N. Sugiyama1、S. Takagi2,4(1.MIRAI-ASET、2.MIRAI-ASRC、3.NICT、4.Univ. of Tokyo, Japan)
[B-1-4]Evaluation of Electron and Hole Mobility at Identical MOS Interfaces by using Metal Source/Drain GOI MOSFETs
K. Morii1、S. Dissanayake1、S. Tanabe1、R. Nakane1、M. Takenaka1、S. Sugahara2、S. Takagi1(1.Univ. of Tokyo、2.Tokyo Tech., Japan)
[B-1-5]Source-to-Drain vs. Band-to-Band Tunneling in Ultra-Scaled DG nMOSFETs with Alternative Channel Materials
Q. Rafhay1、R. Clerc1、G. Pananakakis1、G. Ghibaudo1(1.IMEP, France)
[B-2-1]Recent Progress in Carbon Nanotube Electronics - Modeling, Materials, Devices, Circuits, and Interconnects (Invited)
H. S. P. Wong1(1.Stanford Univ., USA)
[B-2-2]Compact Modeling of Ballistic Nanowire MOSFETs
K. Natori1(1.Univ. of Tsukuba, Japan)
[B-2-3]Investigate the Effects of Channel Materials & Channel Orientations on the Performance of Nanowire FETs
C. S. Koong1、G. Samudra1、G. Liang1(1.National Univ. of Singapore, Singapore)
[B-2-4]Advantages of Densely Packed Multi-Wire Transistors with a Planar Gate Structure and a Low-k Buried Insulator over Planar SOI Devices
M. Ono1、K. Uchida2、T. Tezuka1(1.Toshiba Corp.、2.Tokyo Tech., Japan)
[B-2-5]Modeling and Analysis of Short-Channel Effects in Double-Gate MOSFETs
K. Ishimura1、N. Sadachika1、M. Miura-Mattausch1(1.Hiroshima Univ., Japan)
[B-3-1]Low GIDL Characteristics on Fin-FET with Source/Drain Extension Engineering for 22nm Node Low Power Devices
K. Hayashi1、T. Iwamatsu1、R. Tsuchiya2、K. Ishikawa1、T. Terada1、H. Shinohara1、K. Eikyu1、T. Uchida1、H. Oda1、Y. Inoue1(1.Renesas Tech. Corp.、2.Hitachi, Ltd., Japan)
[B-3-2]Physical and Electrical Design of FinFET based SRAM Bitcell for 22nm Node and Below
S. C. Song1、M. Abu-Rahma1、B. M. Han1、S. S. Yoon1、J. Wang1、W. Yang2、C. Hu2、G. Yeap1(1.Qualcomm Inc.、2.Univ. of California Berkeley, USA)
[B-3-3]Gate-All-Around 4-nm Silicon Nanowire Schottky Barrier MOSFET with 1-D NiSi Source/Drain
J. W. Peng1,2,3、S. J. Lee2、G. C. Albert Liang2、N. Singh1、C. M. Ng3、G. Q. Lo1、D. L. Kwong1(1.Inst. of Microelectronics、2.National Univ. of Singapore、3.Chartered Semiconductor Manufacturing Ltd., Singapore)
[B-3-4]Erbium/Platinum Silicided Gate-All-Around Silicon Nanowire Schottky Source/Drain MOSFETs
E. J. Tan1,2,3、K. L. Pey1、N. Singh2、G. Q. Lo2、D. Z. Chi3、Y. K. Chin1、L. J. Tang2(1.Nanyang Technological Univ.、2.Inst. of Microelectronics、3.Inst. of Materials Res. and Eng., Singapore)
[B-3-5L]Principal Guideline of Stress Design Engineering for Drivability Enhancement and Suppression of Variability in PMOSFET with SiGe S/D
M. Nishikawa1、N. Tamura2、Y. Shimamune2、A. Hatada1、K. Ikeda2、T. Yamamoto2、T. Miyashita2、Y. S. Kim2、T. Kubo1、T. Sukegawa1、M. Fukuda1、K. Sukegawa2、H. Kurata2、M. Kase1、K. Hashimoto1(1.Fujitsu Microelectronics Ltd.、2.Fujitsu Labs. Ltd., Japan)
[B-5-1]Design and Optimization of Gate Sidewall Spacers to Achieve 45nm Ground Rule for High-performance Applications
T. Miyashita1、K. Ookoshi2、A. Hatada2、K. Ikeda1、Y. S. Kim1、M. Nishikawa2、T. Sakoda1、K. Hosaka1、H. Kurata1(1.Fujitsu Labs. Ltd.、2.Fujitsu Microelectronics Ltd., Japan)
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