[OP]Opening Remarks
Tamotsu Hashizume1(1.General Chair, Organizing Committee)
2021 International Conference on Solid State Devices and Materials
Sep 6 - Sep 9, 2021
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2021 International Conference on Solid State Devices and Materials
Sep 6 - Sep 9, 2021
You can search for presentations in this event.
SearchSearch Results(376)
[OP]-Opening Remarks
Mutsuko Hatano1(1.President, The JapanSociety of Applied Physic)
[PL-01 (Plenary)]Electronics 5.0: New Materials and Devices for Edge Intelligence
Tomás Palacios1(1.Massachusetts Institute of Technology)
[PL-02 (Plenary)]History and Evolution of NAND Flash Memory
Masaki Momodomi1(1.KIOXIA Corporation)
[PL-03 (Plenary)]Materials and Device Physics of Hyperfluorescence OLEDs and Future Prospect
Chihaya Adachi1(1.Kyushu University)
[PL-04 (Plenary)]Silicon Based Quantum Computing
Maud Vinet1(1.CEA-Leti)
[AW-01]Award Ceremony (Comment from Award winner)
[AW-02]Comment from Young Researcher Award recipient
Hikaru Kawarazaki(SCREEN Semiconductor Solutions Co., Ltd.)
[AW-03]Comment from Young Researcher Award recipient
Marina Yamaguchi(KIOXIA Corporation)
[AW-04]Comment from Young Researcher Award recipient
Austin Lee Hickman(Cornell University)
[AW-05]Comment from Young Researcher Award recipient
Quentin Wilmart(Univ. Grenoble Alpes, CEA, LETI)
[AW-06]Comment from Young Researcher Award recipient
Mikie Tsuji(University of Tsukuba)
[AW-07]Comment from Young Researcher Award recipient
Taro Sasaki(The University of Tokyo)
[AW-08]Comment from Young Researcher Award recipient
Shutaro Karube(Tohoku University)
[AW-09]Comment from Young Researcher Award recipient
Takuya Wadatsumi(Kobe University)
[PD-01]-
[A-1-01 (Invited)]Recent Progress of FDSOI MOS Technology for Quantum Computing and Perspectives for Scaling up
〇Benoit Bertrand1, Louis Hutin1, Heimanu Niebojewski1, Pierre-André Mortemousque1, Mikaël Cassé1, Gérard Billiot1, Xavier Jehl2, Romain Maurand2, Matias Urdampilleta3, Yann-Michel Niquet2, Silvano De Franceschi2, Tristan Meunier3, Maud Vinet1(1.Univ. Grenoble Alpes, CEA-Leti, 2.Univ. Grenoble Alpes, CEA-IRIG, 3.Univ. Grenoble Alpes, CNRS, Néel Inst.)
[A-1-02]16x8 Quantum Dot Array Operation at Cryogenic Temperatures
〇Noriyuki Lee1, Ryuta Tsuchiya1, Yusuke Kanno1, Toshiyuki Mine1, Yoshitaka Sasago1, Go Shinkai1, Raisei Mizokuchi2, Jun Yoneda3, Tetsuo Kodera2, Chihiro Yoshimura1, Shinichi Saito1, Digh Hisamoto1, Hiroyuki Mizuno1(1.Research & Development Group, Hitachi, Ltd., 2.Department of Electrical and Electronic Engineering, Tokyo Institute of Technology, 3.Tokyo Tech Academy for Super Smart Society, Tokyo Institute of Technology)
[A-1-03]Characterization of Sub-threshold Swing of Si n-MOSFETs over a Temperature Range of 4 K to 300 K
〇Min-Soo Kang1, Kasidit Toprasertpong1, Mitsuru Takenaka1, Shinichi Takagi1(1.The Univ. of Tokyo)
[A-1-04]Effect of Gate Stack Material on Performance and Low-frequency Noise in Si p-MOSFETs at Cryogenic Temperature: Comparison of SiO2/Poly-Si Gate and High-k/Metal Gate
〇Hiroshi Oka1, Takumi Inaba1, Ryo Hashimoto1, Takahiro Mori1(1.AIST)
[A-1-05] Attainment of low subthreshold slope in planar type inversion channel InGaAs NMOSFET with in-situ deposited Al2O3/Y2O3 as gate dielectrics
〇Lawrence Boyu Young1, Jun Liu1, Yen-Hsun Glen Lin1, Hsien-Wen Wan1, Jueinai Kwo2, Minghwei Hong1(1.National Taiwan Univ., 2.National Tsing Hua Univ.)
[A-1-06]Effect of Percolation Path on Temperature Dependence of Threshold Voltage Variability in Bulk MOSFETs
〇TOMOKO MIZUTANI1, KIYOSHI TAKEUCHI1, TAKUYA SARAYA1, HIROSHI OKA2, TAKAHIRO MORI2, MASAHARU KOBAYASHI1,3, TOSHIRO HIRAMOTO1(1.IIS, Univ. of Tokyo, 2.AIST, 3.d.lab, Univ. of Tokyo)
[A-4-01 (Invited)]Technology Enablement for Advanced Logic Nodes using Materials to Systems Co-OptimizationTM Platform
〇Ashish Pal1, El Mehdi Bazizi1(1.Applied Materials)
[A-4-02] Introduction of high tensile strain in Ge-on-Insulator structures by oxidation/annealing at high temperature
〇Xueyang Han1, ChiaTsong Chen1, Cheol-Min Lim1, Kasidit Toprasertpong1, Mitsuru Takenaka1, Shinichi Takagi1(1.Univ. of Tokyo)
[A-4-03]Anisotropic Strain States in Extremely-Thin Body Ge-on-Insulator p-type MOSFET Observed by Oil-Immersion Raman Spectroscopy
〇Ryo Yokogawa1,2, Chia-Tsong Chen3, Kasidit Toprasertpong3, Mitsuru Takenaka3, Shinichi Takagi3, Atsushi Ogura1,2(1.Meiji Univ., 2.MREL, 3.Univ. of Tokyo)
[A-4-04] Low Thermal Budget Epitaxial Lift Off for Ge (111)-on-Insulator Structure
〇Wen-Hsin Chang1, Hsien-Wen Wan2, Yi-Ting Cheng2, Yen-Hsun G. Lin2, Toshifumi Irisawa1, Hiroyuki Ishii1, Jueinai Kwo3, Minghwei Hong2, Tatsuro Maeda1(1.Natl. Inst. of Adv. Indus. Sci. Tech., 2.Grad. Inst. of Appl. Phys. and Dept. of Phys., Natl. Taiwan Univ., 3.Dept. of Phys., Natl. Tsing Hua Univ.)
[A-4-05 (Invited)] GeSn/GeSi Stacked Channel Transistors
Chien-Te Tu1, Bo-Wei Huang1, Chung-En Tsai1, Yi-Chun Liu1, 〇Chee Wee Liu1(1.National Taiwan Univ.)
[A-4-06]Electron Mobility Enhancement in n-GeSn Epitaxial Layers by Tensile Strain
〇Kai-Ying Tien1, Chia-You Liu1, Po-Yuan Chiu1, Yen Chuang1, Hsiang-Shun Kao1, Jiun-Yun Li1,2,3(1.Graduate Inst. of Electronics Eng., National Taiwan Univ., 2.Department of Electrical Eng., National Taiwan Univ., 3.Taiwan Semiconductor Res. Inst.)
[A-4-07] In-situ Deposited HfO2 and Y2O3 on Epi-Si/p-Ge – a Comparative Study of the Interfacial Properties
〇Tien Yu Chu1, Hsien Wen Wan1, Yi Ting Cheng1, Chao Kai Cheng 1, Yu Jie Hong1, Jueinai Kwo2, Minghwei Hong Hong1(1.Granduate Institute of Applied Physics and Department of Physics, National Taiwan Univ., Taipei 10617, 2.Department of Physics, National Tsing Hua Univ., Hsinchu 30013)
[A-5-01] Enhancement of Ferroelectricity in 5-nm HZO Metal-Ferroelectric-Insulator-Semiconductor Technologies by Using Strained TiN Electrode
〇Cheng-Hung Wu1, Kuan-Chi Wang1, Yu-Yun Wang1, Tian-Li Wu1, Chun-Jung Su2, Yao-Jen Lee2, Chenming Hu1,3(1.National Yang Ming Chiao Tung Univ., 2.Taiwan Semiconductor Research Inst., 3.Univ. California, Berkeley )
[A-5-02]Control of HfO2 Crystallizing Phase in UV Nanosecond Pulsed Laser Annealing
〇Toshiyuki Tabata1, Pablo Acosta Alba2, Jérôme Richy2, Marianne Coig2, Pierre-Edouard Raynal1, Fabien Rozé1, Sebastien Kerdilès2(1.Laser Systems & Solutions of Europe (LASSE), 2.Univ. Grenoble Alpes, CEA-LETI)
[A-5-03]Antiferroelectric properties of ALD ZrO2 ultra-thin films: correlation with the crystalline structure
〇Xuan Luo1, Kasidit Toprasertpong1, Mitsuru Takenaka1, Shinichi Takagi1(1.Univ. of Tokyo)
[A-5-04] Carrier Transport properties of Ferroelectric Hf0.5Zr0.5O2 Thin Films in Poling Treatment
〇Yukinori Morita1, Hiroyuki Ota1, Shinji Migita1(1.AIST)
[A-5-05] Investigation and Design of LK-Type Ferroelectric FET for Ultralow-Voltage NVM Applications
〇Bo-Kai Huang1, Wei-Xiang You1, Pin Su1(1.National Yang Ming Chiao Tung Univ.)
[A-6-01 (Invited)] SOI CMOS and SiGe BiCMOS Technologies for RF and mmW Applications
〇Pascal Chevalier1, Sylvie Gachon2, Frédéric Gianesello1, Andrea Pallotta3, Nicolas Planes1, Patrick Scheer1, Benjamin Dormieu1, Andreia Cathelin1, Patrice Garcia1, Nuccio Villa4, Guillaume Bertrand1, Edoardo Brezza1, Elodie Canderle1, Didier Céli1, Philippe Cathelin1, Tulio Chaves de Albuquerque1, Sébastien Crémer1, Nicolas Derrier1, Siddhartha Dhar1, Houssein El Dirani1, Cédric Durand1, Alexis Gauthier1, Nicolas Guitard1, Alain Fleury1, Franck Julien5, Daniel Gloria1, Eric Granger1, Frédéric Paillardet1, Victor Milon1, Stéphane Monfray1, Frédéric Monsieur1, Yannick Mourier1, Isabelle Sicard1, Jacky Uginet1, Nathalie Vulliet1(1.STMicroelectronics, Crolles, 2.STMicroelectronics, Grenoble, 3.STMicroelectronics, Cornaredo, 4.STMicroelectronics, Agrate Brianza, 5.STMicroelectronics, Rousset)
[A-6-02] Potential benefits of S/D HDD activation by melt laser annealing in 3D-integrated top-tier FDSOI FETs
Anne Vandooren1, 〇Toshiyuki Tabata2, Pierre Eyben1, Erik Roseel1, Andriy Hikavyy1, Karim Huet2, Fulvio Mazzamuto2, Eugenio Dentoni Litta1, Naoto Horiguchi1(1.imec, 2.Laser Systems & Solutions of Europe (LASSE))
[A-6-03]Impact of the buried oxide thickness in UV laser heated 3D stacks
Pierre Morin1, 〇Toshiyuki Tabata2, Fabien Rozé 2, Mohamed Saib 1, Hilde Thielens 1, Louis Thuries 2, Karim Huet2, Fulvio Mazzamuto 2(1.imec, 2.Laser Systems & Solutions of Europe (LASSE))
[A-6-04]Novel Optical Pixel Structure for High Sensitivity in CMOS Image Sensor with 0.7μm Pixels
Jonghoon Park1, 〇Taesung Lee1, Yunji Jung1, Junsung Park1, Chunho Park1, Taehan Kim1, Yunki Lee1, Bumsuk Kim1, Jungchak Ahn1(1.Samsung Electronic Co., Ltd.)
[A-6-05]CMOS Image Sensor with Double Patterned 2x1 On-Chip Lens Phase Detection Auto Focus
Dongmin Keum1, 〇Yeaju Jang1, Kwang Hee Lee1, Junsung Park1, Taesung Lee1, Yunki Lee1, Bumsuk Kim1, Jungchak Ahn1(1.Samsung Electronics Co., Ltd.)
[A-6-06]A Robust Single Device MOSFET Series Resistance Extraction Method Considering Horizontal-Field-Dependent Mobility
〇Kiyoshi Takeuchi1, Tomoko Mizutani1, Takuya Saraya1, Masaharu Kobayashi1, Toshiro Hiramoto1(1.Univ. of Tokyo)
[A-6-07]One to two-trap percolation transition of SILC in SiO2/HfO2
〇Andrea - Vici1,2, Robin Degraeve2, João Pedro Bastos2, Ingrid De Wolf2,1(1.KU Leuven, 2.imec)
[A-6-08] TCAD Simulation for Capture / Emission of Carriers by Traps in SiN: Trap-Assisted Tunneling Model Extended for Capture of Carriers Injected via Fowler-Nordheim Tunneling
〇Michiru Hogyoku1, Yoshinori Yokota1, Kazuhito Nishitani1(1.KIOXIA Corp.)
[A-6-09]Distribution Analysis of Minimum Operating Voltage in Fully Depleted SOI SRAM Cells
〇Hongkuan Yu1, Tomoko Mizutani1, Kiyoshi Takeuchi1, Takuya Saraya1, Masaharu Kobayashi1,2, Toshiro Hiramoto1(1.IIS, the University of Tokyo, 2.d.lab, the University of Tokyo)
[A-6-10]Contactless Characterization of SiOx/c-Si by FTIR and μ-PCD applied to pMOS Devices
〇Mickael Lozach1, Sommawan Khumpuang1,2, Shiro Hara1,2(1.Minimal Fab Promoting Organization, 2.National Institute of Advanced Industrial Science and Technology (AIST))
[A-7-01 (Invited)] Enablement of Next Generation Nanosheet Technology
〇Nicolas Loubet1, Curtis Durfee 1, Julien Frougier1, Shogo Mochizuki1, Maruf Bhuiyan 1, Ruqiang Bao 1, Andrew Greene1, Eric Miller1, Indira Seshadri1(1.IBM Research)
[A-7-02]High Density & High Drive Current Elongated SGT Transistor for Logic Circuit Having Process Compatibility with 1.5nm node SGT SRAM
〇Kenichi Kanazawa1, Yisuo Li3, Tetsuo Izawa1, Koji Sakui1, Georg Strof2, Oskar Baumgartner2, Gerhard Rzepa2, Markus Karner2, Zlatan Stanojevic2, Nozomu Harada1(1.Semicon Consulting Ltd., 2.Global TCAD Solutions Ltd., 3.Unisantis Electronics Singapore Pre Ltd.)
[A-7-03] The Impact of Self-Heating Effect on Noise Margin and Propagation Delay
of Complementary FET Inverter
〇Songhan Zhao1, Wangyong Chen1, Linlin Cai1, Gang Du1(1.Institute of Microelectronics Peking University)
[A-7-04]Width Dependence of Drain Current Variability Components in Extremely Narrow GAA Silicon Nanowire MOSFETs down to 2nm Width
〇Zihao Liu1, Tomoko Mizutani1, Takuya Saraya1, Masaharu Kobayashi1, Toshiro Hiramoto1(1.Inst. of Indus. Sci., The Univ. of Tokyo)
[A-7-05]Improvement of performance of Si0.8Ge0.2/SOI p-FinFETs by ultrathin Y2O3 gate stacks with TMA treatment
〇Tsung-En Lee1, Shao-Tse Huang2, Chiung-Yi Yang2, Kasidit Toprasertpong1, Mitsuru Takenaka1, Yao-Jen Lee2, Shinichi Takagi1(1.Univ. of Tokyo, 2.Taiwan Semiconductor Res. Inst.)
[A-7-06] Attainment of Low Dit and Reliable High-Ge-Content Si1-xGex Gate Stacks via Low-Temperature Grown Ultra-Thin Epitaxial Si
〇HsienWen Wan1, Yi-Ting Cheng1, Chao-Kai Cheng1, Yu-Jie Hong1, Tien-Yu Chu1, Chien-Ting Wu2, Jueinai Kwo3, Minghwei Hong1(1.National Taiwan Univ., 2.Taiwan Semiconductor Res. Inst., 3.National Tsing Hua Univ.)
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