2007 International Conference on Solid State Devices and Materials

2007 International Conference on Solid State Devices and Materials

Sep 18 - Sep 21, 2007Tsukuba International Congress Center (EPOCHAL TSUKUBA), Ibaraki, Japan

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International Conference on Solid State Devices and Materials
2007 International Conference on Solid State Devices and Materials

2007 International Conference on Solid State Devices and Materials

Sep 18 - Sep 21, 2007Tsukuba International Congress Center (EPOCHAL TSUKUBA), Ibaraki, Japan

You can search for presentations in this event.

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Search Results(591)

[A-1-2]PMOSFET Vth Modulation Technique using Fluorine Treatment through ALD-TiN Suitable for CMOS Devices

K. Tai, S. Yamaguchi, K. Tanaka, T. Hirano, I. Oshiyama, S. Kazi, T. Ando, M. Nakata, M. Yamanaka, R. Yamamoto, S. Kanda, Y. Tateshita, H. Wakabayashi, Y. Tagawa, M. Tsukamoto, H. Iwamoto, M. Saito, N. Nagashima, S. Kadomura(1.Semiconductor Technology Development Division, Semiconductor Business Group, Sony Corporation)

[A-1-3]Low Threshold Voltage Gate-First pMISFETs with Poly-Si/TiN/HfSiON Stacks Fabricated with PVD-based In-situ Solid Phase Interface Reaction (SPIR) Method

N. Kitano, H. Arimura, S. Horie, T. Hosoi, T. Shimura, H. Watanabe, T. Kawahara, S. Sakashita, Y. Nishida, J. Yugami, T. Minami, M. Kosuda(1.Graduate School of Engineering, Osaka University, 2.Renesas Technology Corporation, 3.Canon ANELVA Corporation)

[A-1-4]Achieving Band Edge Effective Work Function of Gate First Metal Gate by Oxygen Anneal Processes: Low Temperature Oxygen Anneal (LTOA) and High Pressure Oxygen Anneal (HPOA) Processes

C. S. Park, S. C. Song, C. Burham, H. B. Park, H. Niimi, B. S. Ju, J. Barnett, C. Y. Kang, P. Lysaght, G. Bersuker, R. Choi, H. K. Park, H. Hwang, B. H. Park, S. Kim, P. Kirsch, B. H. Lee, R. Jammy(1.UT/Austin, 2.Samsung Assignee, 3.TI Assignee, 4.GIST, Korea, 5.Poongsan Microtec, 6.IBM Assignees)

[A-2-4]Fabrication of HfOxNy dielectrics on Ge from HfNx deposition

Tatsuro Maeda, Yukinori Morita, Shinichi Takagi(1.MIRAI, Advanced Semiconductor Research Center - National Institute of Advanced Industrial Science and Technology (ASRC-AIST), AIST Tsukuba Central 4, 2.The University of Tokyo)

[A-5-1]Study of Dopant Diffusion and Defect Evolution for Advanced Ultra Shallow Junctions based on Atomistic Modeling

T. Noda, W. Vandervorst, S. Felch, V. Parihar, C. Vrancken, S. Severi, T. Y. Hoffmann, A. Falpin, B. van Daele, T. Jannssens, H. Bender, P. Eyben, M. Niwa, R. Schreutelkamp, F. Nouri, P. P. Absil, M. Jurczak, K. De Meyer, S. Biesemans(1.Matsushita Electric Industrial Co., Ltd., 2.IMEC, 3.Applied Materials)

[A-6-1]Effects of O2 Plasma Treatment on the Reliabilities of Metal Gate/High-k Dielectric MOSFETs

Kyong Taek Lee, Chang Yong Kang, Rino Choi, Seung Chul Song, Byoung Hun Lee, Hi-Deok Lee, Yoon-Ha Jeong(1.Dept. of Electronic and Electrical Engineering, Pohang University of Science and Technology (POSTECH), 2.SEMATECH, 3.IBM assignee, 4.Dept. of Electronics Engineering, Chungnam National Univ, Korea, 5.University of Texas at Austin)

[A-7-4]Systematic studies on Fermi level pining of Hf-based high-k gate stacks

K. Shiraishi, Y. Akasaka, G. Nakamura, M. Kadoshima, H. Watanabe, K. Ohmori, T. Chikyow, K. Yamabe, Y. Nara, Y. Ohji, K. Yamada(1.Graduate School of Pure and Applied Sciences, Univ. of Tsukuba, 2.CREST, Japan Science and Technology Agency, 3.Semiconductor Leading Edge Technology Inc., 4.Graduate School of Engineering, Osaka University, 5.Nanotechnology Research Laboratories, Waseda University, 6.National Institute of Materials Science, 7.Present address: Tokyo Electron Inc.)

[A-8-1]Production-Worthy HfSiON Gate Dielectric Fabrication Enabling EOT Scalability Down to 0.86 nm and Excellent Reliability by Polyatomic Layer Chemical Vapor Deposition Technique

Dai Ishikawa, Satoshi Kamiyama, Atsushi Sano, Sadayoshi Horii, Takayuki Aoyama, Yasuo Nara(1.Research Dept. 1, Semiconductor Leading Edge Technologies (Selete), Inc., 2.Research Dept. 2, Semiconductor Equipment System Lab., Hitachi Kokusai Electric Inc.)

[A-8-2]Tinv Scaling and Jg Reducing for nMOSFET with HfSix/HfO2 Gate Stack by Interfacial Layer Formation Using Ozone Water Treatment Process

I. Oshiyama, K. Tai, T. Hirano, S. Yamaguchi, K. Tanaka, Y. Hagimoto, T. Uemura, T. Ando, K. Watanabe, R. Yamamoto, S. Kanda, J. Wang, Y. Tateshita, H. Wakabayashi, Y. Tagawa, M. Tsukamoto, H. Iwamoto, M. Saito, M. Oshima, S. Toyoda, N. Nagashima, S. Kadomura(1.Semiconductor Technology Development Division, Semiconductor Business Group, Sony Corporation, 2.Graduate School of Engineering, University of Tokyo)

[A-8-3]Highly Manufacturable CMOSFETs with Single High-k (HfLaO) and Dual Metal Gate Integration Process

X.P. Wang, M.-F. Li, H.Y. Yu, J.J. Yang, C.X. Zhu, W.S. Hwang, W.Y. Loh, A.Y. Du, J.D. Chen, Albert Chin, S. Biesemans, G.Q. Lo, D.-L. Kwong(1.SNDL, ECE Dept, National University of Singapore, 2.Institute of Microelectronics, Singapore, 3.IMEC, 4.Dept. of Microelectronics, Fudan University, 5.Dept. of Electronics Eng., Nat’l Chiao-Tung Univ.)

[A-8-4]Highly Manufacturable and Cost-effective Single TaxC / HfxZr(1-x)O2 Gate CMOS Bulk Platform for LP Applications at the 45nm Node and Beyond

M. Muller, C. Hobbs, A. Zauner, S. Barnola, T. Salvetat, S. Lhostis, S. Couderc, P. Perreau, D. H. Triyoso, M. Raymond, E. Luckowski, M. Rafik, A. Cathignol, G. Ribes, D. Fleury, K. Romanjek, S. Pokrant, S. Jullian, P. Morin, M. Aminpur, P. Gouraud, C. Laviron, S. Zoll, P. Garnier, F. Salvetti(1.NXP Semiconductors, 2.Freescale, 3.STMicroelectronics, 4.NXP Semiconductors, Research, 5.CEA-LETI, 6.Freescale Semiconductor Inc.)

[A-9-1]Practical Solutions to Enhance EWF Tunability of Ni FUSI Gates on HfO2

X.P. Wang, J.J. Yang, H.Y. Yu, M.-F. Li, J.D. Chen, R.L. Xie, C.X. Zhu, A.Y. Du, P.C. Lim, Andy Lim, Y.Y. Mi, Doreen M.Y. Lai, W.Y. Loh, S. Biesemans, G.Q. Lo, D.-L. Kwong(1.SNDL, ECE Dept, National University of Singapore, 2.Institute of Microelectronics, 3.IMEC, 4.Dept. of Microelectronics, Fudan University, 5.Institute of Material Research and Engineering)

[B-1-4]Pt-germanide Formed by Laser Annealing and Its Application for Schottky Source/Drain MOSFET Integrated with TaN/CVD-HfO2/Ge Gate Stack

Rui Li, S. J. Lee, D. Z. Chi, M. H. Hong, D. -L. Kwong(1.Silicon Nano Device Lab, Department of ECE, National University of Singapore, 2.Institute of Materials Research and Engineering, 3.Laser Microprocessing Lab, Department of Electrical and Computer Engineering, National University of Singapore, 4.Institute of Microelectronics)

[B-1-6]New Observations on the Narrow Width Effect of the Hot Carrier and NBTI Reliabilities in pMOSFETs with Various Types of Strains

S. S. Chung, D. C. Huang, C. S. Lai, C. H. Tsai, P. W. Liu, Y. H. Lin, C. T. Tsai, G. H. Ma, S. C. Chien, S. W. Sun(1.Department of Electronic Engineering, National Chiao Tung University, Taiwan, 2.Chang-Gung University, Taiwan, 3.United Microelectronics Corporation (UMC), Central R&D Division, Taiwan)

[B-3-2]High Performance and Low Leakage CMOS for 45nm Low Power Technology and Beyond

J.-P. Han, Y. M. Lee, H. Utomo, R. Lindsay, M. Eller, J.C. Kim, V. Sardesai, V. Chan, S. Fang, J. Holt, T.N. Adam, H. Zhuang, W. Wille, Z. Lun, H. Wang, T. Dyer, J. Yan, O.J. Kwon, O.S. Kwon, C.W. Lai, T.J. Tang, S.S. Tan, J. Yuan, J. Li, H. Ng, H. Shang, J. Sudijono, D. Schepis, M. Ieong, Y. Li, J.H. Ku, A. Gutmann, M. Hierlemann(1.Infineon Technologies AG, 2.Chartered Semiconductor Manufacturing Limited, 3.IBM Semiconductor Research and Technology Group, 4.Samsung Elec. Co. Alliances at IBM Semiconductor Research and Development Center (SRDC))

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