[A-1-1]Gate Stress Induced Performance Enhancements
Zoran Krivokapic, Qi Xiang, Witek Maszara, Ming-ren Lin(1.AMD, Technology Research Group)
2004 International Conference on Solid State Devices and Materials
Sep 14 - Sep 17, 2004Tower Hall Funabori, Tokyo, Japan
You can search for presentations in this event.
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2004 International Conference on Solid State Devices and Materials
Sep 14 - Sep 17, 2004Tower Hall Funabori, Tokyo, Japan
You can search for presentations in this event.
SearchSearch Results(473)
[A-1-2]Physical Origin of Drive Current Enhancement in Ultra-thin Ge-On-Insulator (GOI) MOSFETs under Full Ballistic Transport
Shin-ichi Takagi(1.Department of Frontier Informatics, Graduate School of Frontier Science, The University of Tokyo)
[A-1-3]Suppression of Boron Penetration from S/D Extension to improve Gate Leakage Characteristics and Gate-Oxide Reliability for 65nm node CMOS and beyond
T. Hayashi, T. Yamashita, K. Shiga, K. Hayashi, H. Oda, T. Eimori, M. Inuishi, Y. Ohji(1.Renesas Technology Corp., Wafer Process Engineering Development Dept.)
[A-1-4]Dopant Profile Design Methodology for 65 nm Generation via Inverse Modeling
Takuji Tanaka, Mitsuru Yamaji, Hiroyuki Kanata, Yukio Tagawa, Shigeo Satoh, Toshihiro Sugii(1.FUJITSU Ltd.)
[A-1-5]Strained-Si for CMOS 65nm node : Si0.8Ge0.2 SRB or “Low Cost” approach ?
F. Boeuf, F. Payet, N. Casanova, Y. Campidelli, N. Villani, O. Kermarrec, J.M. Hartmann, N. Emonet, F. Leverd, P. Morin, C. Perrot, V. Carron, C. Laviron, F. Arnaud, S. Jullian, D. Bensahel, T. Skotnicki(1.STMicroelectronics, 2.CEA-LETI, 3.Philips Semiconductors)
[A-2-1]Fully Silicided NiSi Gates on HfSiON Gate Dielectrics for Low Power Application
Kenzo Manabe, Kensuke Takahashi, Taeko Ikarashi, Ayuka Morioka, Heiji Watanabe, Takuya Yoshihara, Toru Tatsumi(1.System Devices Research Laboratories, NEC Corporation)
[A-2-2]Weak Temperature Dependence of Non-Coulomb Scattering Component of HfAlOx-Limited Inversion Layer Mobility in n+poly-Si/HfAlOx/SiO2 n-MOSFETs
N. Yasuda, H. Hisamatsu, H. Ota, A. Toriumi(1.MIRAI-ASET, 2.MIRAI-ASRC, 3.Department of Materials Science, The University of Tokyo)
[A-2-3]High Mobility Dual Metal Gate MOS Transistors with High-k Gate Dielectrics
Kensuke Takahashi, Kenzo Manabe, Ayuka Morioka, Taeko Ikarashi, Takuya Yoshihara, Heiji Watanabe, Toru Tatsumi(1.System Devices Research. Laboratories, NEC Corporation)
[A-2-4]Temperature effects of constant bias stress on NFETs with Hf-based gate dielectric
Rino Choi, Byoung Hun Lee, Chadwin D. Young, Jang Hoan Sim, Gennadi Bersuker(1.International SEMATECH, 2.IBM assignee)
[A-2-5]Charge Trapping Characteristics of Hafnium Based High-κDielectrics with Various Metal Electrodes
Chadwin D. Young, Gennadi Bersuker, Huang-Chun Wen, George A. Brown, Prashant Majhi(1.International SEMATECH (ISMT), 2.Phillips Assignee)
[A-2-6]Dependences of Device Performances on Interfacial Layer Materials of High-k MISFETs due to Wave Function Penetration into Gate Dielectrics
Mizuki Ono, Akira Nishiyama(1.Advanced LSI Technology Laboratory, Corporate R&D Center, Toshiba Corporation)
[A-3-1]Research and Development of Organic Electroluminescent Devices and Application for Plastic Information Devices
Yutaka Ohmori, Hirotake Kajii(1.Osaka University, Center for Advanced Science and Innovation (CASI))
[A-3-2]Enhancement of luminance yield of blue light organic light emitting diode
Chiu-Yen Su, Fuh-Shyang Juang, Shen-Jhou Jhang, Yen-Fong Chen(1.Institute of Electrical Engineering, Kun Shan University of Science and Technology, 2.Institute of Electro-Optical and Materials Science, National Huwei University of Science and Technology)
[A-3-3]Efficient red electrophosphorescent devices based on starburst molecules
Yuichi Hino, Hirotake Kajii, Yutaka Ohmori(1.Center for Advanced Science and Innovation (CASI), Osaka University)
[A-3-5]Lifetime property of flexible organic light emitting diodes with plasma polymer barrier layers
Sunyoung Sohn, Samil Kho, Kyuhyung Kim, Donggeun Jung(1.Department of Physics, Institute of Basic Science, and Brain Korea 21 Physics Research Division, Sungkyunkwan University)
[A-4-1]Enhanced Luminance Efficiency from Organic Light-Emitting Diodes with 2D Photonic Crystal
Masatoshi Kitamura, Satoshi Iwamoto, Yasuhiko Arakawa(1.Research Center of Advanced Science and Technology, University of Tokyo, 2.Institute of Industrial Science, University of Tokyo)
[A-4-2]The transfer of emission site in polymer LEDs with increasing voltages
Noriyuki Takada, Kiyohiko Tsutsumi, Toshihide Kamata(1.Photonics Research Institute, National Institute of Advanced Industrial Science and Technology)
[A-4-3]VERTICAL TYPE ORGANIC LIGHT EMITTING TRANSISTOR USING THIN-FILM ZnO
Hiroyuki Iechi, Masatoshi Sakai, Masakazu Nakamura, Kazuhiro Kudo(1.Ricoh Co. Ltd, Environmental Technology R&D Center, 2.Chiba University, Faculty of Engineering, 3.Optoelectronic Industry Tech. Development Association)
[A-4-4]Preparation of polymer-based light-emitting field-effect transistors
Tomo Sakanoue, Eiichi Fujiwara, Ryo Yamada, Hirokazu Tada(1.The Graduate University for Advanced Studies, Department of Structural Molecular Science, 2.Institute for Molecular Science, National Institutes of Natural Science, 3.JST-CREST, Japan Science and Technology Agency)
[A-4-5]Organic Bi-Function Matrix Array
Yohsuke Matsushita, Hiroyuki Shimada, Takuya Miyashita, Miki Shibata, Shigeki Naka, Hiroyuki Okada, Hiroyoshi Onnagawa(1.Faculty of Engineering, Toyama University, 2.Innovation Plaza Tokai, Japan Science and Technology Agency)
[A-4-6]Theoretical Investigation of the Electronic Properties of PEDOT: PSS Conducting Polymer on Indium Tin Dioxide (ITO) Surface: an Accelerated Quantum Chemical Molecular Dynamics Method
Chen Lv, Xiaojing Wang, Agalya Govindasamy, Hideyuki Tsuboi, Michihisa Koyama, Momoji Kubo, Akira Miyamoto(1.Department of Applied Chemistry, Graduate School of Engineering, Tohoku University, 2.New Industry Creation Hatchery Center, Tohoku University, 3.PRESTO, Japan Science and Technology)
[A-5-1]Successful CMOS Operation of Dopant-Segregation Schottky Barrier Transistors (DS-SBTs)
A. Kinoshita, Y. Tsuchiya, A. Yagishita, K. Uchida, J. Koga(1.Advanced LSI Technology Laboratory, Corporate R&D Center, Toshiba Corporation, 2.Process and Manufacturing Engineering Center, Semiconductor Company, Toshiba Corporation)
[A-5-2]Optimization of Low Power and High Speed DTM for Embedded RAM Applications
H. Tashiro, K. Tsunoda, A. Sato, T. Nakanishi, H. Tanaka(1.Fujitsu Laboratories Ltd.)
[A-5-3]Realization of n-type and p-type Si-Microprobe Array Using In-Situ Doping with Selective Vapor-Liquid-Solid (VLS) Growth Method
Md. Shofiqul Islam, Hiroshi Ishino, Takeshi Kawano, Hidekuni Takao, Kazuaki Sawada, Makoto Ishida(1.Department of Electrical and Electronic Engineering Toyohashi University of Technology)
[A-5-4]A New Well Capacity Adjusting Scheme for High Sensitivity, Extended Dynamic Range CMOS Imaging Pixel Sensors
Cheng-Hsiao Lai, Yueh-Ping Yu, Ya-Chin King(1.Microelectronic Laboratory, Semiconductor Technology Application Research (STAR) Group, Department of Electrical Engineering, National Tsing-Hua University)
[A-7-1]Investigation of Degradation model for Ultra -thin Gate Dielectrics
Hiroko Mori, Hideo Ehara, Naoyoshi Tamura, Chioko Kaneta, Hideya Matsuyama, Ken Shono(1.FUJITSU LSI Quality Assurance Div., 2.FUJITSU Laboratories Ltd.)
[A-7-2]Thermal Stability of Metal Gate Work Functions
H.Y. Yu, Chi Ren, J.F. Kang, Yee-Chia Yeo, Daniel S.H. Chan, M.F. Li, Dim-Lee Kwong(1.Silicon Nano Device Lab, Dept. of Electrical & Computer Eng., National University of Singapore, 2.Institute of Microelectronics, 3.Dept. of ECE, The University of Texas)
[A-7-3]Robust TiN/AHO/HSG-Cylinder Capacitor for High Density DRAMs
S.G. Kim, C.S. Hyun, D. Park, H.J. Moon, H.C. Kim, S.J. Kim, T.H. Cho, H.J. Kang, S.M. Jeong, S.W. Lee, S.H. Lee, J.G. Suk, B.K. Lim, Y.S. Jeon, S.G. Jeon, K.Y. Lee, K.S. Oh, W.S. Lee(1.DRAM Process Architecture Team, 2.Fab Team 3, 3.SRAM/Flash Process Architecture Team, Memory Division, Samsung Electronics Co., Ltd.)
[A-7-4L]Effect of Strain on Static and Dynamic NBTI of pMOSFETs
Hong-Nien Lin, Horng-Chih Lin, Tiao-Yuan Huang, Chih-Hsin Ko, Chung-Hu Ge, C.-C. Lin, Chien-Chao Huang(1.Institute of Electronics, National Chiao-Tung University, 2.National Nano Device Laboratories, 3.Taiwan Semiconductor Manufacturing Company, Ltd.)
[A-8-1]Ge and SiGe for High Performance MOSFETs and Integrated Optical Interconnects
Krishna C. Saraswat, Chi On Chui, Tejas Krishnamohan, Ali K. Okyay, Hyoungsub Kim, Paul McIntyre(1.Department of Electrical Engineering, Stanford University, 2.Department of Materials Science and Engineering, Stanford University)
[A-8-2]A Novel STI Process from the View Point of Total Strain Process Design for 45nm Node Devices and Beyond
M. Ishibashi, K. Horita, M. Sawada, M. Kitazawa, M. Igarashi, T. Kuroi, T. Eimori, K. Kobayashi, M. Inuishi, Y. Ohji(1.Process Technology Development Div, Renesas Technology Corp.)
[A-8-3]Theoretical Investigation of Electrical Performance and Band Structure of P-MOSFETs with Si1-xGex Source/Drain Stressors
Kah-Wee Ang, Yong-Tian Hou, Jagar Singh, Ming-Fu Li, Yee-Chia Yeo(1.Department of Electrical and Computer Engineering, National University of Singapore, 2.Institute of Microelectronics)
[A-8-4]In-Plane Anisotropy of MOS Inversion Layer Mobility on Silicon (100), (110) and (111) surfaces
H. Irie, K. Kita, K. Kyuno, A. Toriumi(1.Department of Materials Science, School of Engineering, The University of Tokyo)
[A-9-1]Nanoscale Device Simulation at the Scaling Limit and Beyond
Anisur Rahman, Gerhard Klimeck, Nizami Vagidov, Timothy B. Boykin, Mark Lundstrom(1.School of ECE, Network for Computational Nanotechnology Purdue University, 2.Department of EE, State University of New York, 3.Department of Elec. and Comp. Engineering, University of Alabama)
[A-9-2]Nanoscale Quasi-Ballistic MOSFETs in Reflection-Transmission Model
Kenji Natori, Takashi Kurusu(1.Institute of Applied Physics, University of Tsukuba)
[A-9-3]Quantitative Understanding of Mobility Degradation in High Effective Electric Field Region in MOSFETs with Ultra-thin Gate Oxides
Takamitsu Ishihara, Junji Koga, Shin-ichi Takagi(1.Advanced LSI Technology Laboratory, Research and Development Center, Toshiba Corporation, 2.Department of Frontier Informatics, Graduate School of Frontier Science, The University of Tokyo)
[A-9-4]Determination of tunnel mass and thickness of gate oxide including poly-Si/SiO Si/SiO2 interfacial transition layers
Hiroshi Watanabe, Daisuke Matsushita, Kouichi Muraoka(1.Advanced LSI Technology Laboratory)
[A-10-1]Halo and LDD Engineering for Multiple VT High Performance Analog Devices in 0.13μm CMOS Technology
J. C. Guo, W.Y. Lien, C. C. Liur, C.M. Wu(1.Department of Electronics Engineering, National Chiao Tung University, 2.Research Development Center, Taiwan Semiconductor Manufacturing Corp.)
[A-10-2]A Large-Signal MOSFET Model Based on Transient Carrier Response for RF Circuits
Kazufumi Watanabe, Koji Kotani, Akinobu Teramoto, Shigetoshi Sugawa, Tadahiro Ohmi(1.Graduate School of Engineering, Tohoku University, 2.New Industry Creation Hatchery Center, Tohoku University)
[A-10-3]A Quantum Mechanical Corrected SPICE Model for Ultrathin Oxide MOSFETs’ Gate Tunneling Current Simulation
Yiming Li, Shao-Ming Yu, Jam-Wem Lee(1.Department of Computational Nanoelectronics, National Nano Device Laboratories, 2.Microelectronics and Information Systems Research Center, National Chiao Tung University, 3.Department of Computer and Information Science, National Chiao Tung University)
[B-1-1]Electrical Characterization of High-k Gated MOSFETs and Interfaces
T.P. Ma(1.Yale University Center for Microelectronic Materials and Structures, and Department of Electrical Engineering)
[B-1-2]Electron Mobility Degradation Mechanisms in HfSiON MISFETs under the Real Operating Condition
Ryosuke Iijima, Mariko Takayanagi, Takamitsu Ishihara, Takeshi Yamaguchi, Akira Nishiyama(1.Advanced LSI Technology Laboratory, Corporate Research & Development Center, Toshiba Corporation, 2.SoC Research & Development Center, Toshiba Corporation Semiconductor Company)
[B-1-3]Nitrogen profile engineering in the interfacial SiON for HfAlOx gate dielectric
Riichiro Mitsuhashi, Kazuyoshi Torii, Hiroshi Ohji, Takaaki Kawahara, Atsushi Horiuchi, Hitoshi Takada, Masashi Takahashi, Hiroshi Kitajima(1.Semiconductor Leading Edge Technologies)
[B-1-4]Direct comparison of ZrO2 and HfO2 on Ge substrate in terms of the realization of ultra-thin high-k gate stacks
Yoshiki Kamata, Yuuichi Kamimuta, Tsunehiro Ino, Akira Nishiyama(1.Advanced LSI Technology Laboratory, Corporate R&D Center, Toshiba Corporation)
[B-1-5]1.2nm HfSiON/SiON stacked gate insulators for 65nm-node MISFETs
Motofumi Saitoh, Nobuyuki Ikarashi, Heiji Watanabe, Shinji Fujieda, Hirohito Watanabe, Toshiyuki Iwamoto, Ayuka Morioka, Takashi Ogura, Masayuki Terai, Koji Watanabe, Makoto Miyamura, Toru Tatsumi, Taeko Ikarashi, Koji Masuzaki, Yukishige Saito, Yuko Yabe(1.System Devices Research Laboratories, NEC Corp.)
[B-2-1]Carbon nanotube technologies for future ULSI via interconnects
Yuji Awano, Mizuhisa Nihei, Shintaro Sato, Akio Kawabata, Daiyu Kondo, Mari Ohfuti, Naoki Yokoyama(1.Fujitsu Limited, 2.Nanotechnology Research Center, Fujitsu Laboratories Ltd.)
[B-2-2]Interface Adhesion and Phase Formation in Cu Interconnect
J. Koike, A. Sekiguchi, M. Wada(1.Dept. of Materials Science, Tohoku University)
[B-2-3]Etch-byproduct Pore Sealing for ALD -TaN Deposition on Porous Low-k Film
Akira Furuya, Eiichi Soda, Hiroshi Okamura, Nobuyuki Ohtsuka, Miyoko Shimada, Naofumi Ohashi, Shinichi Ogawa(1.Semiconductor Leading Edge Technologies Inc. (Selete))
[B-2-4]Recovery of Process-induced Damages of Porous Silica Low- k Films by TMCTS Vapor Annealing
Y. Oku, N. Fujii, Y. Seino, Y. Takasu, H. Takahashi, Y. Sonoda, T. Goto, H. Miyoshi, S. Takada, T. Kikkawa(1.MIRAI, Association of Super-Advanced Electronics Technologies (ASET), 2.MIRAI, Advanced Semiconductor Research Center, National Institute of Advanced Industrial Science and Technology, 3.Advanced Semiconductor Research Center, National Institute of Advanced Industrial Science and Technology, 4.Research Center for Nanodevices and Systems, Hiroshima University)
[B-2-5]A Metallurgical Prescription Suppressing Stress-induced Voiding (SIV) in Cu lines
Mari Abe, Naoya Furutake, Shinobu Saito, Naoya Inoue, Yoshihiro Hayashi(1.System Devices Research Laboratories, NEC Corporation)
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