[A-0-1]Future CMOS Scaling-Approaching the Limits?
Robert H. Dennard(1.IBM T. J. Watson Research Center)
1996 International Conference on Solid State Devices and Materials
Aug 26 - Aug 29, 1996Pacifico Yokohama, Yokohama, Japan
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1996 International Conference on Solid State Devices and Materials
Aug 26 - Aug 29, 1996Pacifico Yokohama, Yokohama, Japan
You can search for presentations in this event.
SearchSearch Results(298)
[A-0-2]An Attempt for Industrial-Academic-Governmental Joint Research in the Basic Studies of Device, Material and Process -- Research on Ultimate Manipulation of Atoms and Molecules at the National Institute for Advanced Interdisciplinary Research --
Yasuharu SUEMATSU(1.National Institute for Advanced Interdisciplinary Research, Agency of Industrial Science and Technology, Ministry of International Trade and Industry)
[A-1-1]Atomic-Scale and Hierarchical Modeling for Nano-Electronics
Robert W. Dutton, Edwin C. Kan, Shinji Onga, Takako Okada(1.Center for Integrated Systems, Stanford University, 2.ULSI Research Center, Toshiba)
[A-1-2]New Method of Extracting Inversion Layer Thickness and Charge Profile and Its Impact on Scaled MOSFETs
Tetsu TANAKA, Toshihiro SUGII, Chenming HU(1.Fujitsu laboratories LTD., 2.Department of Electrical Engineering and Computer Sciences, University of California at Berkeley)
[A-1-3]A Novel Conductance Measurement Technique for Profiling the Lateral LDD n-Doping Concentrations of Submicron MOS Devices
Steve S. Chung, G. H. Lee, S. M. Cheng, M. S. Liang(1.Department of Electronic Engineering, National Chiao Tung University, 2.Taiwan Semiconductor Manufacturing Co.)
[A-1-4]A New Observation of the Reverse Short Channel Effect in Submicron n-MOSFET by Using Gate-Induced Drain Leakage Current Measurement
S. M. Cheng, Steve S. Chung, M. S. Liang(1.Department of Electronic Engineering, National Chiao Tung University, 2.Taiwan Semiconductor Manufacturing Co.)
[A-2-1]An Approach for Migrating to Low Voltage and Low Power ULSIs
Eiji Takeda(1.Technology Marketing Operation Semiconductor & IC Division, Hitachi Ltd.)
[A-2-2]Proposal of Pseudo Source and Drain MOSFETs and Evaluation for 10-nm Gate MOSFETs
H. Kawaura, T. Sakamoto, T. Baba, Y. Ochiai, J. Fujita, S. Matsui, J. Sone(1.Fundamental Research Laboratories, NEC Corporation)
[A-2-3]Self-Aligned Control of Threshold Voltages in 0.1 μm nMOSFETs
H. Kurata, T. Sugii(1.Fujitsu Laboratories Ltd.)
[A-2-4]Three-Terminal Silicon Esaki Tunneling Device
Junji KOGA, Akira TORIUMI(1.ULSI Research Laboratories, Toshiba Corporation)
[B-1-1]Lithographic Technologies for 1-Gb DRAMs and Beyond
Shinji Okazaki(1.Semiconductor Development Center Semiconductor & Integrated Circuits Div. Hitachi Ltd.)
[B-1-2]Effects of Cleavage on Local Cross-Sectional Stress Distribution in Trench Isolation Structure
Atsushi YAGISHITA, Tomohiro SAITO, Satoshi MATSUDA, Yukihiro USHIKU(1.Microelectronics Engineering Laboratories, Toshiba Corporation)
[B-1-3]RIE-Lag Reduction by NH3 Addition in Aluminum Alloy Etching under BCl3/Cl2 Chemistry
Michinari YAMANAKA, Hideo NAKAGAWA, Masafumi KUBOTA(1.Semiconductor Research Center, Matsushita Electric Industrial Co., Ltd.)
[B-1-4]Double Spacer LOCOS Process with Shallow Recess of Silicon for 0.20 μm Isolation
Byung-Jin Cho, Se-Aug Jang, Tae-Sik Song, Seung-Ho Pyi, Jong-Choul Kim(1.Memory R&D Div., HYUNDAI Electronics Ind. Co. Ltd.)
[B-1-5]CMP with Pad-Press Ring for Superior Uniformity Performance
Mikio Nishio, Tomoyasu Murakami, Masashi Hamanaka(1.Semiconductor Research Center, Matsushita Electric Industrial, Co., Ltd., 2.Kyoto Research Laboratory, Matsushita Electronics Corporation)
[B-1-6]Polysilicon Encapsulated LOCOS for Deep Submicron CMOS Lateral Isolation
Goncal Badenes, Rita Rooyackers, Ingrid De Wolf, Ludo Deferm(1.IMEC)
[B-2-1]Selective Nucleation Based Epitaxy(SENTAXY): A Novel Approach for Thin Film Formation
Hideya KUMOMI, Takao YONEHARA(1.Canon Inc., Device Development Center)
[B-2-2]Deposition and Characterization of Silicon-Germanium Alloy Thin Films on Oxide
Rafael Reif(1.Microsystems Technology Laboratories Massachusetts Institute of Technology)
[B-2-3]Low Temperature Epitaxy of Si and SiGe by the Novel Centrifugal LPE Technique
Mitsuharu KONUMA(1.Max-Planck-Institut fur Festkorperforschung Max-Planck-Institut fur Metallforschung)
[B-2-4]A Proposed Atomic-Layer-Deposition of Germanium on Si(100)
Takuya KITAMURA, Satoshi SUGAHARA, Tomonori NAGAI, Yasutaka UCHIDA, Masakiyo MATSUMURA(1.Department of Physical Electronics, Tokyo Institute of Technology, 2.Department of Electronics and Information Science, Teikyo University of Science and Technology)
[Sympo.V-1]Extended Defects in II-VI Blue Green Laser Diodes
R. L. Gunshor, J. Han, A. V. Nurmikko(1.School of Electrical Engineering, Purdue University, 2.Division of Engineering & Physics Department, Brown University)
[Sympo.V-2]Characterization of ZnMgSSe-Based Wide-Gap Laser Diodes
Kazushi NAKANO, Akira ISHIBASHI(1.Sony Corporation Research Center)
[Sympo.V-3]Fundamentals of the Nitride Based Laser Diode
I. Akasaki, S. Sota, H. Sakai, H. Amano(1.Department of Electrical and Electronic Engineering, Meijo University)
[Sympo.V-4]Bluish-Purple InGaN Multi-Quantum Well Structure Laser Diodes
Shuji NAKAMURA(1.Department of Research and Development, Nichia Chemical Industries, Ltd.)
[Sympo.V-5]Defect Issues in III-V Alloy Semiconductors and Their Influence on the Degradation of Optical Devices
Osamu UEDA(1.Fujitsu Laboratories Ltd.)
[Sympo.V-6]Optical Degradation of InGaN/AlGaN LED on Sapphire Substrate Grown by MOCVD
Takashi EGAWA, Hiroyasu ISHIKAWA, Takashi JIMBO, Masayoshi UMENO(1.Research Center for Micro-Structure Devices, Nagoya Institute of Technology, 2.Department of Electrical and Computer Engineering, Nagoya Institute of Technology)
[Sympo.V-7]Characterization and Control of MBE-ZnSe/GaAs(100) Substrate Interface and Regrown ZnSe/ZnSe Homointerface
Yuji YAMAGATA, Kohji FUJIWARA, Takayuki SAWADA, Kazuaki IMAI, Kazuhiko SUZUKI, Naohito KIMURA, Isao TSUBONO(1.Department of Applied Electronics, Hokkaido Institute of Technology)
[Sympo.V-8]MOVPE Growth of High Quality GaN/InGaN Single Quantum Well Structure Using Misoriented SiC Substrate
Akihiko ISHIBASHI, Hidemi TAKEISHI, Nobuyuki UEMURA, Masahiro KUME, Yuzaburoh BAN(1.Semiconductor Research Center, Matsushita Electric Industrial Co., Ltd.)
[Sympo.V-9]Excitonic Properties in ZnSe/MgS Superlattices
Hiroyuki NASHIKI, Hidekazu KUMANO, Hideki SUZUKI, Toshio OBINATA, Katsuhiro UESUGI, Jun'ichiro NAKAHARA, Ikuo SUEMUNE(1.Research Institute for Electronic Science, Hokkaido University, 2.Department of Physics, Hokkaido University)
[D-1-1]High Speed InP-Based ICs for a Fiber-to-Microwave Link
Y. K. Chen, J. Lin, D. Humphrey, R. K. Montgomery, R. Hamm, J. Weiner, R. Kopf, F. Ren, J. Lothian, R. Ryan, D. Sivco, A. Y. Cho(1.Bell Laboratories, Lucent Technologies)
[D-1-2]Highly Selective Wet-Etching Using Adipic Acid for Uniform Damage-Free Process of InAlAs/InGaAs HEMTs
Katsuhiko HIGUCHI, Hiroyuki UCHIYAMA, Takashi SHIOTA, Makoto KUDO, Tomoyoshi MISHIMA(1.Central Research Lab., Hitachi, Ltd.)
[D-1-3]New Technologies of a WSi Base Electrode and a Heavily-Doped Thin Base Layer for High-Performance InGaP/GaAs HBTs
Tohru OKA, Kiyoshi OUCHI, Kazuhiro MOCHIZUKI, Tohru NAKAMURA(1.Central Research Laboratory, Hitachi, Ltd.)
[D-1-4]InGaP/GaAs Sub-Square-Micron Emitter HBT with fmax＞100 GHz
Koji HIRATA, Tomonori TANOUE, Hiroshi MASUDA, Hiroyuki UCHIYAMA, Akihisa TERANO(1.Hitachi ULSI Engineering, Corp., 2.Central Research Laboratory, Hitachi Ltd.)
[D-2-1]Photonic Sampling of Ultrafast Electronic Devices: Bridging the Measurement Gap
Jeremy ALLAM(1.Hitachi Cambridge Laboratory Cavendish Laboratory)
[D-2-2]Kelvin Probe Force Microscopy for Potential Distribution Measurement of Cleaved Surface of GaAs Devices
Masashi ARAKAWA, Shigeru KISHIMOTO, Takashi MIZUTANI(1.Department of Quantum Engineering, Nagoya University)
[D-2-3]The Change of Mo/GaAs Schottky Characteristics by the Forward Gate Current
Tomoyuki OHSHIMA, Ryoji SHIGEMASA, Tamotsu KIMURA(1.Semiconductor Technology Laboratory, Oki Electric Industry Co., Ltd.)
[D-2-4]Enhancement of Schottky Barrier Heights on Indium Phosphide-Based Materials by In-Situ Electrochemical Process and Its Mechanism
Teketomo SATO, Shouichi UNO, Tamotsu HASHIZUME, Hideki HASEGAWA(1.Research Center for Interface Quantum Electronics and Graduate School of Electronics and Information Engineering, Hokkaido University)
[A-3-1]Metal CVD Technology for ULSI Applications: The Aluminum Route
Andreas KNORR, Jonathan FALTERMEIER, Robert TALEVI, Heidi GUNDLACH, Kaushik Arun KUMAR, Gregory G. PETERSON, Alain E. KALOYEROS(1.New York State Center for Advanced Thin Film Technology and Department of Physics, the University at Albany-SUNY)
[A-3-2]Self-Aligned Passivation Technology for Copper Interconnection Using Copper-Aluminum Alloy
Nobuyoshi Awaya, Toshio Kobayashi(1.NTT LSI Laboratories)
[A-3-3]Gap-Filling of Cu Employing Self-Sustained Sputtering with ICP Ionization
Takanori ICHIKI, Toshiaki KIKUCHI, Atsushi SANO, Shoso SHINGUBARA, Yasuhiro HORIIKE(1.Department of Electrical & Electronics Engineering, Toyo University, 2.Department of Electrical Engineering, Hiroshima University)
[A-3-4]A Study of Via-Electromigration Failure in Multilevel Interconnection with High Temperature Sputtered Aluminum
Makiko Kageyama, Keiichi Hashimoto, Hiroshi Onoda(1.VLSI R&D Center, Oki Electric Industry Co., Ltd.)
[A-4-1]Ultra-Shallow Doping for Si Sub-0.1 μm Devices
S. Matsumoto(1.Department of Electrical Engineering, Keio University)
[A-4-2]The Role of Hydrogen during Rapid Vapor-Phase Doping Analyzed by FTIR-ATR
Yukihiro KIYOTA, Seiji SUZUKI, Taroh INADA(1.Central Research Laboratory, Hitachi Ltd., 2.College of Engineering, Hosei University)
[A-4-3]Channel Doping Engineering with Indium as an Alternative p-Type Dopant
Yeong-Taek Lee, Ki-Whan Song, Byung-Gook Park, Jong Duk Lee(1.Inter-University Semiconductor Research Center School of Electrical Engineering, Seoul Nat'l Univ.)
[A-4-4]Influence of Ion Energy on Carrier Activation and Source/Drain Parasitic Resistance in Low-Energy Ion Implantation for 0.15-μm MOSFETs
Akio NISHIDA, Eiichi MURAKAMI, Shin'ichiro KIMURA(1.Central Research Laboratory, Hitachi Ltd.)
[A-5-1]A Novel Technique for Ultrathin CoSi2 Layers: Oxide Mediated Epitaxy
Rymond T. Tung(1.Tokyo Institute of Technology, Research Center for Quantum Effect Electronics)
[A-5-2]Anomalous Junction Leakage Behavior of Ti-SALICIDE Contacts on Ultra-Shallow Junctions
Atsuko SAKATA, Masato KOYAMA, Haruko AKUTSU, Iwao KUNISHIMA, Mitsuo KOIKE, Mitsuhiro TOMITA(1.Microelectronics Engineering Laboratory, ULSI Research Laboratories, Environmental Engineering Laboratory, TOSHIBA Corporation)
[A-5-3]Advanced Ti Salicide Technology for High Performance Quarter-Micron Logic LSIs
Jun Suenaga, Hirofumi Sumi, Kazuhiro Tajima, Atsushi Horiuchi, Michihiro Kanno, Yutaka Okamoto(1.MOS Process dept., MOS LSI div., Semiconductor Company, Sony Corporation)
[A-5-4]Reconditioning-Free Polish for Inter-Layer-Dielectric Planarization
K. Nakamura, S. Kishii, Y. Arimoto(1.Fujitsu Laboratories Ltd.)
[A-5-5]Reliability of Low-Parasitic-Capacitance Multilevel Interconnection Using Surface-Densified Low-ε Organic Spin-on Glass
Takeshi FURUSAWA, Yoshio HOMMA(1.Central Research Laboratory, Hitachi, Ltd.)
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