[P-0-1]High Temperature Superconductors and Its Application
Shoji Tanaka(1.Department of Physics Tokai University)
1988 International Conference on Solid State Devices and Materials
Aug 24 - Aug 26, 1988Keio Plaza Hotel, Tokyo, Japan
You can search for presentations in this event.
Search
1988 International Conference on Solid State Devices and Materials
Aug 24 - Aug 26, 1988Keio Plaza Hotel, Tokyo, Japan
You can search for presentations in this event.
SearchSearch Results(171)
[P-0-2]Imaging with the STM and the AFM
Calvin F. QUATE(1.Edward L. Ginzton Laboratory Stanford University)
[A-1-1]Experimental Technology and Performance of 0.1μm Gate-Length Low Temperature Operation MOSFETs
G. A. Sai-Halasz(1.IBM Research Division, T. J. Watson Research Center)
[A-1-2]Fully Symmetrical Cooled-CMOS on (110) Plane
Masaaki Aoki, Kazuo Yano, Toshiaki Masuhara, Katsuhiro Shimohigashi(1.Central Research Laboratory, Hitachi Ltd.)
[A-1-3]High Temperature Operated Enhancement-Type β-SiC MOSFET
Hiroo Fuma, Atsushi Miura, Hiroshi Tadano, Susumu Sugiyama, Mitsuharu Takigawa(1.Toyota Central Res. & Dev. Labs., Inc.)
[A-1-4]A New Device Structure Utilizing Atomic Layer Doping (ALD) Technology in Si Systems
Ken YAMAGUCHI, Kiyokazu NAKAGAWA, Yasuhiro SHIRAKI(1.Central Research Laboratory, Hitachi Ltd., 2.Research Center for Advanced Science and Technology University of Tokyo)
[A-1-5]A Complete Self-aligned-gate LID-MOS Technology
Hiroshi Inokawa, Toshio Kobayashi(1.NTT LSI Laboratories)
[A-2-1]High Power Insulated Gate Bipolar Transistors (IGBTs)
H. Ohashi, A. Nakagawa, M. Hideshima(1.Toshiba R&D Center, 2.Toshiba Microelectronics Center)
[A-2-2]TILBW Bipolar Power Switching Transistor
Andrei SILARD, Gabriel NANI(1.Department of Electronics, Polytechnic Institute, 2.IPRS-Baneasa (Enterprise for Radio Components & Semiconductors))
[A-2-3]500V Lateral Double Gate Bipolar-Mode MOSFET(DGIGBT) Dielectrically Isolated by Silicon Wafer Direct-Bonding(DISDB)
Akio Nakagawa, Yoshihiro Yamaguchi, Kiminori Watanabe(1.Toshiba Corporation)
[A-2-4]6000V Double Gate GTOs
Tsuneo OGURA, Akio NAKAGAWA, Katsuhiko TAKIGAMI, Masaki ATSUTA, Yoshio KAMEI(1.Research and Development Center, Toshiba Corp.)
[A-2-5]Drain Current Optimization for a Very High Voltage Fast Switch Device with Bipolar Mode FET Structure
P. G. Fallica, G. Ferla, A. Galluzzo, S. Musumeci, S. Bellone, G. Cocorullo(1.ST - Microelectronics, 2.University of Naples, 3.IRECE-CNR)
[A-3-1]Lateral Autodoping Suppression by Selective Epitaxy Capping and Its Application in High Speed BiCMOS
Tzu-Yin Chiu, Kwing F. Lee, Maureen Y. Lau, Sean N. Finegan, Mark D. Morris, Alexander M. Voshchenkov(1.AT&T Bell Laboratories)
[A-3-2]Very-Low-Temperature Epitaxial Silicon Growth by Low-Kinetic-Energy Particle Bombardment
Tadahiro Ohmi, Kiyohiko Matsudo, Tadashi Shibata Takeshi Ichikawa, Hiroshi Iwabuchi(1.Department of Electronics, Faculty of Engineering Tohoku University)
[A-3-3]Low Temperature CVD Technique for Crystalline Si Deposition
T. Fujii, H. Araki, M. Ohkuni, Y. Tarui(1.Department of Electronic Engineering, Tokyo University of Agriculture & Technology, 2.VLSI Development Laboratories, Sharp Corporation)
[A-3-4]Novel Highly Conductive Polycrystalline Silicon Films Reducing Processing Temperature Down to 650℃
T. Kobayashi, S. Iijima, S. Aoki, A. Hiraiwa(1.Central Research Laboratory, Hitachi Ltd.)
[A-4-1]Selective Growth of Polycrystalline Silicon by Laser-Induced Cryogenic CVD
Takeshi TANAKA, Koji DEGUCHI, Seiichi MIYAZAKI, Masataka HIROSE(1.Department of Electronics, Hiroshima Institute of Technology, 2.Department of Electrical Engineering, Hiroshima University)
[A-4-2]Effects of Magnetic Fields and Excited Plasma Species on Silicon Oxide Film Formation by Microwave Plasma CVD
Takuya Fukuda, Kazuo Suzuki, Yasuhiro Mochizuki, Michio Ohue, Naohiro Momma, Tadashi Sonobe(1.Hitachi Research Laboratory and Hitachi Works, Hitachi Ltd.)
[A-4-3]Growth of SiO2 Thin Film by Photo-CVD Using 123nm VUV Light
Kohji INOUE, Masanori OKUYAMA, Yoshihiro HAMAKAWA(1.Department of Electrical Engineering, Faculty of Engineering Science, Osaka University)
[A-4-4]Reaction Mechanisms with Synchrotron Radiation-Stimulated Etching of Si and SiO2
Jun-ichi Takahashi, Yuichi Utsumi, Tsuneo Urisu(1.NTT LSI Laboratories)
[A-5-1]Microcharacterization and Novel Device Applications of Semiconductor-Metal Eutectic Composites
B. M. DITCHEK, B. G. YACOBI(1.GTE Laboratories Incorporated)
[A-5-2]A High Integrity and Low Resistance Ti-Polycide Gate Using a Nitrotgen Ion Implanted Buffer Layer
K. Kobushi, S. Okada, S. Kameyama, K. Tsuji(1.Basic Research Laboratory, Semiconductor Research Center, Matsushita Electric Industrial Co., Ltd.)
[A-5-3]Tungsten Plug Technology: Substituting Tungsten for Silicon Using Tungsten Hexaflouride
Nobuyoshi Kobayashi, Masayuki Suzuki, Masayoshi Saitou(1.Central Research Laboratory, Hitachi Ltd.)
[A-5-4]Evaluation of Laser CVD Tungsten for Gate Electrode
Hideaki Matsuhashi, Satosi Nishikawa, Seigo Ohno(1.Semiconductor Technology Laboratory, OKI Electric Industry Co., Ltd.)
[A-5-5]TiSi2 and TiN Formation by Ti-Ion Implantation and Their Application to MOS Devices
Yasuhisa Omura, Hiroshi Inokawa, Katsutoshi Izumi(1.NTT LSI Laboratories)
[A-7-1]High-Dose and MeV-Energy Ion Implantation into Si for Buried-Layer Formation
Tadashi SUZUKI, Masao TAMURA, Kiyonori OHYU, Nobuyoshi NATSUAKI(1.Central Research Laboratory, Hitachi, Ltd.)
[A-7-2]Annealing of Defects by High Energy Ion Implantation
Yoshiko NIKI, Soichi NADAHARA, Masaharu WATANABE(1.ULSI Research Center, Toshiba Co.)
[A-7-3]Lateral Diffusion of Dopants beyond Preamorphized Region
T. IZAWA, M. KASE, H. MORI, K. KOBAYASHI, M. NAKANO(1.Advanced Tech. Division and Process Development Division, FUJITSU LTD.)
[A-7-4]Impurity Doping into Single and Poly Crystalline Silicon by a Large Area Ion Doping Technique
Akihisa YOSHIDA, Masatoshi KITAGAWA, Kentaro SETSUNE, Takashi HIRAO(1.Central Research Laboratories, Matsushita Electric Industrial Co., Ltd.)
[A-8-1]Excimer Laser Doping for Sub-Micron Device Fabrication
H. Tomita, M. Negishi, T. Sameshima, H. Hayashi, S. Usui(1.Sony Research Center and, 2.Sony Semiconductor Group R. and D. Department)
[A-8-2]Photo-Enhanced Boron-Doping in Low-Temperature Silicon Epitaxy and Its FTIR Study
S. Watanabe, T. Yamazaki, Y. Nara, T. Ito(1.FUJITSU LABORATORIES LTD., ATSUGI)
[A-8-3]A New Dopant Diffusion Modeling Based on Point Defect Kinetics
Takako KASHIO, Koichi KATO(1.ULSI Research Center, Toshiba Corporation)
[A-9-1]Low Temperature Operation of a Si HBT
H. Fujioka, T. Deguchi, K. Takasaki, K. Kawashima, Y. Ban(1.FUJITSU LTD.)
[A-9-2]A 5 Gb/s 4 Bit Shift Register with 0.5 μm WNx-gate GaAs MESFETs
K. Ishida, T. Matsunaga, S. Miyano, A. Kameyama, N. Toyoda(1.ULSI Research Center, Toshiba Corporation)
[A-9-3]4bit A/D and 8bit D/A Converters Implemented with AlGaAs/GaAs HBTs
Y. Kuriyama, M. Ishibe, M. Asaka, M. Obara, S. Shimizu(1.Toshiba Research and Development Center)
[A-9-4]Analysis of Two-Dimensional Effects on Switching Delay Time for Emitter Coupled Logic Circuits
Toshihiko HAMASAKI, Tetsunori WADA(1.ULSI Research Center, Toshiba Corporation)
[A-9-5]Characteristics of Bipolar Transistors with Various Depth n+ Buried Layers Formed by High Energy Ion Implantation
A. Tamba, Y. Kobayashi, T. Suzuki, N. Natsuaki(1.Hitachi Research Laboratory, Hitachi Ltd., 2.Central Research Laboratory, Hitachi Ltd.)
[A-9-6]Characterization of Silicon Bipolar Devices Fabricated Using Very-Low-Temperature Plasma Process
Tadashi SAITOH, Masao KONDO, Tsuyoshi UEMATSU, Masao TAMURA(1.Central Research Laboratory, Hitachi, Ltd.)
[A-9-7]The Integration of Double-Polysilicon NPN Transistors in an Analog BiCMOS Process
W. Josquin, D. de Lang, M. van Iersel, J. van Dijk, A. van de Goor, E. Bladt(1.Philips Research Laboratories)
[B-1-1]Radiation Response of MOS Structures Containing Oxides Grown in a NF3/O2 Oxidizing Ambient
Eronides F. da Silva, Jr., Yasushiro Nishioka, T. -P. Ma(1.Universidade Federal de Pernambuco Departamento de Fisica, 2.Cidade Universitaria)
[B-1-2]An Experimental Study of Hot Carrier Temperature in Submicron pMOSFETs
Kazuyuki Saito, Akira Yoshii(1.NTT LSI Laboratories)
[B-1-3]Experimental Evidence for Hole-Induced Interface State Generation under High Field Tunneling Current Stressing
Yoshio OZAWA, Masao IWASE, Akira TORIUMI(1.ULSI Research Center, Toshiba Corporation)
[B-1-4]A Reliable Profiled Lightly-Doped Drain(PLD) Cell for High Density Submicron EPROMS and Flash EEPROMS
Kuniyoshi YOSHIKAWA, Masaki SATO, Yoichi OHSHIMA(1.Semiconductor Device Engineering Laboratory, TOSHIBA Corporation)
[B-1-5]New Phenomena in MNOS Retention Characteristics and Their Application to Memory Device Design for Megabit EEPROM's
Sin-ichi Minami, Yoshiaki Kamigaki, Ken Uchida, Koichi Nagasawa, Kazunori Furusawa, Takeshi Furuno, Takaaki Hagiwara, Masaaki Terasawa(1.Central Research Laboratory, Hitachi Ltd., 2.Musashi Works, Hitachi Ltd., 3.Hitachi VLSI Engineering Corp.)
[B-1-6]Inter-Poly SiO2/Si3N4 Capacitor Films 5nm Thick for Deep Submicron LSIs
J. Yugami, T. Mine, S. Iijima, A. Hiraiwa(1.CENTRAL RESEARCH LABORATORY, HITACHI, LTD.)
[C-1-1]Effect of Annealing on the SOI Structure Formed by Large Dose Oxygen Implantation
Nan-Xiang Chen, Wei Miao, Zhong-Lie Wang, Chang Huang(1.Inst. of Low Energy Nuclear Physics, Beijing Normal University, 2.Shaanxi Eishan Micro-Electronics Institute)
[C-1-2]High Crystalline Quality Si Film Formation on Lattice-matched Mixed Oxide (SrxBa1-xO)/Si(111) Stacked Structure
Yuichi Kado, Yoshinobu Arita(1.NTT LSI Laboratory)
[C-1-3]Crystal Defect Study of Solid Phase Epitaxially Grown Si Surrounded by SiO2 Structures
Eiichi Murakami, Masao Tamura, Kikuo Kusukawa, Masahiro Moniwa, Terunori Warabisako, Masanobu Miyao(1.Central Research Laboratory, Hitachi, Ltd.)
[C-1-4]Recrystallization Mechanism for Solid Phase Growth of Poly-Si Films on Quartz Substrates
Akira NAKAMURA, Fumiaki EMOTO, Eiji FUJII, Yasuhiro UEMOTO Atsuya YAMAMOTO, Kohji SENDA, Gota KANO(1.Electronics Research Laboratory Matsushita Electronics Corporation)
[C-1-5]Performance and Microstructural Analysis of 3D Circuits Fabricated in E-Beam Recrystallized SOI
Haroon AHMED, Richard A. McMAHON(1.Microelectronics Research Laboratory, Department of Physics, Cambridge University)
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