[P-1]Japanese Management in an Era of Change
Jiro Ushio(1.Ushio Inc.)
1999 International Conference on Solid State Devices and Materials
Sep 21 - Sep 24, 1999Nihon Toshi Center Kaikan, Tokyo, Japan
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1999 International Conference on Solid State Devices and Materials
Sep 21 - Sep 24, 1999Nihon Toshi Center Kaikan, Tokyo, Japan
You can search for presentations in this event.
SearchSearch Results(297)
[P-2]Interconnect Limits on Gigascale Integration
James D. Meindl
[P-3]R&D Challenges and Chance in Today's Japan
Seiki Ogura(1.Halo LSI Design and Device Technology Inc.)
[A-1-1]Effects of the Scaling on n+/p Junction Leakage Characteristics
T. Fukai, K. Takeuchi, T. Mogami(1.ULSI Research Lab., Silicon Systems Research Labs., NEC)
[A-1-2]Leakage Mechanism of Local Junctions Forming Main or Tail Mode of DRAM Retention Characteristics
Shuichi Ueno, Yasuo Inoue, Masahide Inuishi(1.ULSI development center, MITSUBISHI electric corporation)
[A-1-3]Characteristics of Dual Polymetal (W/WNx/Poly-Si) Gate CMOS for 0.1 μm DRAM Technology
Yong-Hae Kim, Sung-Keun Chang, Seon-Soon Kim, Jun-Gi Choi, Sang-Hee Lee Dae-Hee Hahn, Hyung-Duck Kim(1.Semiconductor Advanced Research Division, Hyundai Electronics Industries)
[A-1-4]A New Observation of the Width Dependent Hot Carrier Effect in Shallow-Trench-Isolated P-MOSFET's
Steve S. Chung, W.-J. Yang, C.-M. Yih, J.-J. Yang(1.Department of Electronic Engineering, National Chiao Tung University, 2.Worldwide Semiconductor Manufacturing Co.)
[A-1-5]Stress Induced Subthreshold Current Hump in Short Gate-Length pMOSFET's with Shallow Trench Isolation
L. P. Chiang, L. Y. Huang, N. K. Zous, Tahui Wang(1.Department of Electronics Engineering, National Chiao-Tung University)
[A-1-6]Optimized Shallow Trench Isolation Technology for DRAM Embedded Logic Process
T. Yamazaki, K. Ohno, N. Tsuchiya, T. Gocho(1.Process Development Department, LSI R&D Group, Core Technology & Network Company, Sony Corp.)
[A-2-1]Transport Properties in Sub-10-nm-gate EJ-MOSFETs
Hisao Kawaura, Toshitsugu Sakamoto, Toshio Baba(1.Fundamental Research Laboratories, NEC Corporation)
[A-2-2]Influence of Intrinsic Current Fluctuation in Very Small Si-MOSFETs
Nobuyuki Sano, Kenji Natori, Kazuya Matsuzawa, Mikio Mukai(1.Institute of Applied Physics, University of Tsukuba, 2.Semiconductor Technology Academic Research Center (STARC))
[A-2-3]Excess Noise in Sub-Micron Silicon FET:Transport Theory and Device Optimization
Luiz M. Franca-Neto, James S. Harris(1.Center for Integrated Systems, Stanford University)
[A-2-4]Simulation of Temperature Dependence of Microwave Noise in MOS Transistors
Michael Obrecht, Tajinder Manku(1.RF Technology Group, Electrical and Computer Engineering Department, University of Waterloo)
[B-1-1]Device Design Considerations for Sub-50 nm CMOS
Tsu-Jae King(1.Department of Electrical Engineering and Computer Sciences University of California)
[B-1-2]Dependence of Sub-Threshold Hump and RNWE Characteristics on the Gate Length by TED
Jong-Wan Jung, Jong-Min Kim, Jeong-Hwan Son, Shin-Young Chung, Young-Jong Lee, Hyun-Cheol Kim, Kyung-Ho Lee(1.LG Semicon Co., Ltd.)
[B-1-3]Anomalous Hot Carrier Degradation of nMOSFETs with an Ultra-Shallow Source/Drain Extension
Kaori Nakamura, Eiichi Murakami, Shin'ichiro Kimura(1.ULSI Research Department, Central Research Laboratory, Hitachi Ltd.)
[B-1-4]The Impact of Nitrogen Implantation at LDD(NIL) on Deep Sub-Micron CMOS Devices
Sung-Kwon Hong, Sang-Gi Lee, Jae-Gyung Ahn, Dae-Gwan Kang, Jeong-Mo Hwang(1.LG Semicon Co., Ltd, R&D Division)
[B-2-1]Oxide Mediated Solid Phase Epitaxy (OMSPE) of Silicon: A New Low Temperature Epitaxy Technique Using Intentionally Grown Native Oxide
I. Mizushima, Y. Mitani, K. Miyano, S. Kambayashi(1.Microelectronics Engineering Laboratory, R&D Center, Toshiba Corporation)
[B-2-2]High Performance Buried Channel-pFETs Using Elevated Source/Drain Structure with Self-Aligned Epitaxial Silicon Sliver (SESS)
J. H. Lee, S. C. Lee, N. Y. Kwak, I. S. Yeo, C. Y. Yeom, S. Ritterbush, S. K. Lee, C. T. Kim(1.Semiconductor Advanced Research Div., HYUNDAI Electronics Industries Co., 2.Applied Materials Korea, 3.Applied Materials)
[B-2-3]Study of an Elevated Drain Fabrication Method for Ultra Shallow Junction
M. Nakano, H. Kotaki, K. Sugimoto, T. Okumine, F. Yoshioka, S. Kakimoto, K. Ohta, N. Hashizume(1.Advanced Technology Research Laboratories, Sharp Corporation)
[B-2-4]Novel Impurity Activation Technology Using Gate Poly-Si Oxidation
N. Morosawa, H. Kotaki, S. Kakimoto, M. Yamanaka, K. Ohta, N. Hashizume(1.Advanced Technology Research Laboratories, Sharp Corporation)
[B-2-5]The Device Degradation Due to Contamination from STI Filling Material
S. J. Hong, M. H. Park, S. H. Hong, H. K. Kang, S. I. Lee(1.Semiconductor R&D Center, Samsung Electronics Co., Ltd.)
[C-1-1]OMVPE Growth of AlGaInN for UV Light Emitters
Jung Han, Mary H. Crawford(1.Sandia National Laboratories)
[C-1-2]Effects of Strain on Highly-Mismatched AlGaN/GaN Multiple Quantum Wells
Norio Iizuka, Nobuo Suzuki(1.Advanced Discrete Semiconductor Technology Laboratory, Toshiba Corporation)
[C-1-3]Investigation of Growth Process of GaN Film on Sapphire by Computational Chemistry
Takayuki Onozu, Yusaku Inaba, Seiichi Takami, Momoji Kubo, Akira Miyamoto, Yasushi Iyechika, Takayoshi Maeda(1.Department of Materials Chemistry, Graduate School of Engineering, Tohoku University, 2.Tsukuba Research Laboratory, Sumitomo Chemical Co. Ltd.)
[C-1-4]The Effect of Isoelectronic In-Doping on the Structural and Optical Properties of (Al)GaN Grown by Metal Organic Vapor Phase Epitaxy
Shigeo Yamaguchi, Michihiko Kariya, Shugo Nitta, Hiroshi Amano, Isamu Akasaki(1.Department of Electrical and Electronic Engineering, Meijo University, 2.High-Tech Research Center, Meijo University)
[C-1-5]Arsenic Surfactant and Incorporation Effects on Cubic GaN Grown by Metalorganic Vapor Phase Epitaxy
Tokuharu KIMURA, Seikoh YOSHIDA, Jun WU, Hiroyuki YAGUCHI, Kentaro ONABE, Yasuhiro SHIRAKI(1.Department of Applied Physics, The University of Tokyo, 2.Yokohama R&D Laboratories, The Furukawa Electric Co., Ltd., 3.Department of Electrical and Electronic Systems, Saitama University, 4.Research Center for Advanced Science and Technology (RCAST), The University of Tokyo)
[C-1-6]Bandgap Energy and Effective Mass of BGaN
T. Honda, M. Shibata, M. Kurimoto, M. Tsubamoto, J. Yamamoto, H. Kawanishi(1.Department of Electronic Engineering, Kohgakuin University)
[C-2-1]Application of Pressure Grown GaN Substrates to Epitaxy
S. Porowski(1.High Pressure Research Center Polish Academy of Sciences)
[C-2-2]Growth of Bulk GaN Single Crystals by the Pressure-Controlled Solution Growth Method
Takayuki Inoue, Yoji Seki, Osamu Oda, Satoshi Kurai, Yoichi Yamada, Tsunemasa Taguchi(1.Central R&D Laboratory, Japan Energy Corporation, 2.Faculty of Engineering, Yamaguchi University)
[C-2-3]Hydride Vapor Phase Epitaxy of GaN on NdGaO3 Substrate and Realization of Freestanding GaN Wafers with 2-inch Scale
Akihiro WAKAHARA, Takenori YAMAMOTO, Kouji ISHIO, Akira YOSHIDA, Youji SEKI, Osamu ODA(1.Dept. of Electrical and Electronic Eng., Toyohashi Univ. of Technology, 2.Central Research Lab., Japan Energy Co.)
[C-2-4]Optical Recombination Processes in High Quality GaN Films and InGaN Quantum Wells Grown on FIELO-GaN Substrates
A. Atsushi Yamaguchi, Yasunori Mochizuki, Masashi Mizuta(1.Fundamental Research Laboratories, Optoelectronics and High Frequency Device Research Laboratories, NEC Corporation)
[C-2-5]Nitridation of GaP Surfaces by Rf Nitrogen Radicals and by ECR Nitrogen Plasma
Shin-Ya Ootomo, Tamotsu Hashizume, Hideki Hasegawa(1.Research Center for Interface Quantum Electronics, and Graduate School of Electronics and Information Engineering, Hokkaido University)
[D-1-1]Quantum Computation - Theory and Experiments
A. Ekert(1.Centre for Quantum Computation Clarendon Laboratory, University of Oxford)
[D-1-2]A Novel Solid-State Quantum Bit in Single-Cooper-Pair Device
Yasunobu Nakamura, Yuri A. Pashkin, Jaw-Shen Tsai(1.NEC Fundamental Research Laboratories, 2.CREST, Japan Science and Technology Corporation (JST))
[D-1-3]A High-Speed, Silicon-Based Few-Electron Memory Gain Cell
Andrew C. Irvine, Zahid A. K. Durrani, Haroon Ahmed(1.Microelectronics Research Centre, University of Cambridge, Cavendish Laboratory)
[D-1-4]Sub-μm Silicon SETs on Self-Undulated Hyper-Thin SOI Films
K. Uchida, J. Koga, R. Ohba, S. Takagi, A. Toriumi(1.Advanced LSI Technology Laboratory, Toshiba Corporation)
[D-2-1]Single Electron Memory Devices Based on Silicon Nanocrystals Fabricated by Very High Frequency Plasma Deposition
Amit Dutta, Yoshinori Hayafune, Shigeo Hatatani, Shunri Oda(1.Research Center for Quantum Effect Electronics, Tokyo Institute of Technology)
[D-2-2]Experimental Analysis of Carrier Charging Characteristics in Si Nanocrystal Floating Gate Memory
Ryuji Ohba, Naoharu Sugiyama, Junji Koga, Ken Uchida, Akira Toriumi(1.Advanced LSI Technology Laboratory, TOSHIBA Corporation)
[D-2-3]Charging States of Si Quantum Dots as Detected by AFM/Kelvin Probe Technique
Naoji Shimizu, Mitsuhisa Ikeda, Eiji Yoshida, Seiichi Miyazaki, Masataka Hirose(1.Department of Electrical Engineering, Hiroshima University)
[D-3-1]Matched Filter Type SET Circuit for Room Temperature Operation
Kazuya Masu, Satoshi Shimano, Kazuo Tsubouchi(1.Research Institute of Electrical Communication, Tohoku University)
[D-3-2]Novel Single Electron Logic Circuit Family Constructed with Signal Transmission Structures
Kouichirou Yamamura, Yoshiyuki Suda(1.Venture Business Laboratory, Faculty of Technology, Tokyo University of Agriculture and Technology)
[D-3-3]Proposal of Analytical Single-Electron Transistor Model and Its Implication for Realistic Circuit Operation
K. Uchida, K. Matsuzawa, J. Koga, R. Ohba, S. Takagi, A. Toriumi(1.Advanced LSI Technology Laboratory, Toshiba Corporation)
[D-3-4]The Multi-Tunnel Junction Single Electron Memory: Architecture and Simulation
Lionel Palun, Jacques Gautier(1.Laboratoire d'Electronique, de Technologie et d'Instrumentation, Commissariat a l'Energie Atomique)
[E-1-1]Key Circuits Based on Innovative Design Concepts
Werner Weber, Roland Thewes, Stefan Jung, Christl Lauterbach, Peter Lampacher(1.Infineon Technologies, Corporate Research)
[E-1-2]A Wide-Bandwidth-Output Direct Digital Synthesizer with Plural Delay Generators
Hideyuki Nosaka, Yo Yamaguchi, Masahiro Muraguchi(1.NTT Network Innovation Laboratories)
[E-1-3]Electrical Characteristics of Polysilicon CMOS Analog and Driver Circuits for Intelligent IGBTs
Tomoko Matsudai, Tsutomu Kojima, Akio Nakagawa(1.Advanced Discrete Semiconductor Technology Laboratories, Toshiba Corporation)
[E-1-4]Emulation of Quantum Computing by Parallel Finite Impulse Responses
Shin-ichi O'uchi, Minoru Fujishima, Koichiro Hoh(1.Department of Information and Communication Engineering, Graduate School of Engineering, Department of Frontier Informatics, Graduate School of Frontier Sciences, The University of Tokyo)
[E-2-1]A Pattern Matching Processor Using Analog-Digital Merged Architecture Based on Pulse Width Modulation
Hiroyuki Nakamoto, Makoto Nagata, Takashi Morie, Atsushi Iwata(1.Faculty of Engineering, Hiroshima University)
[E-2-2]A Stochastic Association Circuit Using PWM Chaotic Signals
Toshio Yamanaka, Takashi Morie, Makoto Nagata, Atsushi Iwata(1.Faculty of Engineering, Hiroshima University)
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