[P-1]SSDM 30th Anniversary Memorial Talk, Past, Present and Future of Solid State Devices
Shoji TANAKA(1.Superconductivity Research Laboratory Inernational Superconductivity Technology Center)
1998 International Conference on Solid State Devices and Materials
Sep 7 - Sep 10, 1998International Conference Center Hiroshima, Hiroshima, Japan
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1998 International Conference on Solid State Devices and Materials
Sep 7 - Sep 10, 1998International Conference Center Hiroshima, Hiroshima, Japan
You can search for presentations in this event.
SearchSearch Results(249)
[P-2]The Future of the IT Industry and Japan's Role
Tadahiro Sekimoto(1.Chairman of the Board, NEC Corporation)
[P-3]Self Assembled Quantum Dots and Device Prospects
P. M. Petroff, W. Schoenfeld, T. Lundstrom, N. Horiguchi(1.Materials Department, University of California)
[A-1-1]High Performance n/p Junction Characteristics Using High Temperature RTA in Conjunction with H2 Treatment
S. Miyazaki, K. Hamada, T. Kitano(1.ULSI Device Development Laboratories, NEC Corporation)
[A-1-2]Lateral Diffusion Distance Measurement for 40-80 nm Junctions by Etching/TEM-EELS Method
Y. Kunimune, N. Nishio, N. Kodama, H. Kikuchi, T. Toda, A. Mineji, S. Shishiguchi, S. Saito(1.ULSI Device Development Laboratories, NEC Corporation)
[A-1-3]Sticking Configuration of Boron Atoms from B2H6 on Silicon during Rapid Vapor-Phase Doping
Yukihiro Kiyota, Hideaki Tanaka, Taroh Inada(1.Central Research Laboratory, Hitachi, 2.College of Engineering, Hosei University)
[A-1-4]Boron Segregation to {311} Defects Induced by Self-Implantation Damage in Si
Jianxin Xia, Tomoya Saito, Ryangsu Kim, Takenori Aoki, Yoshinari Kamakura, Kenji Taniguchi(1.Department of Electronics and Information Systems, Osaka University)
[A-1-5]Hydrogen-Enhancing Boron Penetration in P-MOS Devices during SiO2 Chemical Vapor Deposition
Takayuki Aoyama, Kunihiro Suzuki, Hiroko Tashiro, Yoko Tada, Yuji Kataoka, Hiroshi Arimoto, Kei Horiuchi(1.Fujitsu Laboratories Ltd.)
[A-1-6]Quantitative Evaluation of Dopant Loss in Low Energy As Implantation for Low-Resistive, Ultra Shallow Source/Drain Formation
M. Koh, K. Egusa, H. Furumoto, K. Shibahara, S. Yokoyama, M. Hirose(1.RCNS, Hiroshima University)
[A-2-1]Charge-Free and Dopant Dependence-Free Etching Processes Using Non-Maxwellian Electron Energy Distributions in Ultra-High-Frequency Plasma
Seiji Samukawa, Hiroto Ohtake, Ko Noguchi(1.Silicon Systems Research Laboratories, 2.ULSI Device Development Laboratories, NEC Corporation)
[A-2-2]Self-Limiting Atomic-Layer Selective Deposition of Silicon Nitride by Temperature-Controlled Method
Kenji Ooba, Yoshimitsu Nakashima, Anri Nakajima, Shin Yokoyama(1.Research Center for Nanodevices and Systems, Hiroshima University)
[A-2-3]Ultra-Low-Temperature Formation of Si Nitride Film by Direct Nitridation Employing High-Density and Low-Energy Ion Bombardment
Yuji Saito, Katsuyuki Sekine, Masaki Hirayama, Tadahiro Ohmi(1.Department of Electronic Engineering, Graduate School of Engineering, Tohoku University)
[A-2-4]New PentaCoordinated Si(PCS) Model for SiN CVD Mechanism
Shigehiko Saida, Yoshitaka Tsunashima(1.Microelectronics Engineering Laboratory, TOSHIBA Corp.)
[A-2-5]Formation of Very Thin Epitaxial Al2O3 Pre-Layer with Very Smooth Surface on Si(111) Using Protective Oxide Layer
Young-Chul Jung, Hiroyuki Miura, Makoto Ishida(1.Department of Electric and Electronic Engineering, Toyohashi University of Technology)
[B-1-1]Implementation of "System On a Chip" Merging DRAM and Analog with High Performance 0.35nm Logic Device
Sunil Yu, Jong Shik Yoon, Hyae Ryoung Lee, Chul-Soon Kwon, Dong Woo Kim, Won Chul Kim, Chang-Sik Choi(1.LSI TD, System LSI Business, Samsung Electronics Co. Ltd.)
[B-1-2]Trap Assisted Leakage Mechanism of 'worst' Junction in Giga-bit DRAM Using Negative Word-Line Voltage
Hiroshi SUZUKI, Manabu KOJIMA, Yasuo NARA(1.Fujitsu Laboratories Ltd.)
[B-1-3]Silicide-Extension Technology for High-Density Embedded SRAM Cells in 0.18um-CMOS Generation and Beyond
K. Matsui, K. Noda, K. Inoue, T. Itani, H. Iwasaki, T. Yoshii, T. Tanigawa(1.ULSI Device Development Laboratory, NEC Corporation)
[B-1-4]Optimization of Giga-bit DRAM Cell Transistors by Channel and Drain Engineering
M. Kojima, H. Suzuki, T. Miyashita, H. Anzai, T. Nagata, K. Takahashi, M. Sato, Y. Nara(1.Fujitsu Laboratories Ltd.)
[B-1-5]An Analytical Delay Model for Read Operation at Any Position on DRAM Bit Lines
Hongchin Lin, Chia-Hsiang Sha, Shyh-Chyi Wong(1.Dept. of Electrical Engineering, National Chung-Hsing University, 2.Institute of Electrical Engineering, Feng-Chia University)
[B-1-6]Scaling Law for Secondary Cosmic-Ray Neutron-Induced Soft-Errors in DRAMs
Shigeo Satoh, Yoshiharu Tosaka, Toru Itakura(1.Fujitsu Laboratories Ltd.)
[B-2-1]A System Chip Innovation by the Ferroelectric Memory Technology
Isao Matsumoto(1.Device Technology Div. ULSI Research and Development Headquarters, ROHM CO., LTD.)
[B-2-2]Chemica Vapor Deposition of Ru and Its Application in (Ba, Sr)TiO3 Capacitors for Future DRAM
Tomonori Aoyama, Masahiro Kiyotoshi, Soichi Yamazaki, Kazuhiro Eguchi(1.Microelectronics Engineering Laboratory, Toshiba Corporation)
[B-2-3]Electrical Properties of (Ba, Sr)TiO3 Films on Ru Bottom Electrodes Prepared by ECR Plasma CVD at Extremely Low Temperature and RTA
Shuji SONE, Reiko AKAHANE, Koji ARITA, Hisato YABUTA, Shintaro YAMAMICHI, Masaji YOSHIDA, Yoshitake KATO(1.ULSI Device Development Laboratories, NEC Corporation, 2.Fundamental Research Laboratories, NEC Corporation)
[B-2-4]New Practical Model for Endurance Degradation Analysis of Ferroelectric Capacitors
T. Eshita, Y. Arimoto(1.Fujitsu Laboratories Limited)
[B-2-5]Conformal Step Coverage of (Ba, Sr)TiO3 Films Prepared by Liquid Source CVD Using Ti(t-BuO)2(DPM)2
Takaaki Kawahara, Shigeru Matsuno, Mikio Yamamuka, Masayoshi Tarutani, Takehiko Sato, Tsuyoshi Horikawa, Fusaoki Uchikawa, Kouichi Ono(1.Advance Technology R & D Center, Mitsubishi Electric Corporation)
[C-1-1]Magneto-Optical Study of Single InGaAs Quantum Dot
Y. Toda, K. Suzuki, O. Moriwaki, M. Nishioka, Y. Arakawa(1.Institute of Industrial Science, University of Tokyo)
[C-1-2]Light Emission from Individual Self-Assembled InAs/GaAs Quantum Dots Excited by Tunneling Current Injection
Katsuhiko Yamanaka, Kenji Suzuki, Satomi Ishida, Yasuhiko Arakawa(1.Institute of Industrial Science, University of Tokyo)
[C-1-3]Lateral Composition Modulation Induced Structural Anisotropy in InP/GaInP Quantu Dot System
Hong-Wen Ren, Mitsuru Sugisaki, Shigeo Sugou, Kenichi Nishi, A. Gomyo, Yasuaki Masumoto(1.Single Quantum Dot Project, ERATO, JST, c/o Optoelectronics and High Freq. Device Res. Labs. NEC Corp., 2.Optoelectronics and High Frequency Device Research Labs. NEC Corp., 3.Institute of Physics, University of Tsukuba)
[C-1-4]Three-Dimensionally Confined Nanostructures Grown by MBE on Square-and Triangular-Hole Patterned GaAs (311)A Substrates
Z. C. Niu, R. Notzel, U. Jahn, H.-P. Schonherr, J. Fricke, K. H. Ploog(1.Paul Drude Institute for Solid State Electronics)
[C-1-5]Infrared Photodetector with Self-Organized InAs Quantum Dots
Taehee Cho, Jongwook Kim, Jaeung Oh, Jungwoo Choe, Songcheol Hong(1.Opto-Electronics Research Center, Dept. of EE., KAIST, 2.Research Center for Electronic Materials & Components, Dept. of EE., Hanyang University, 3.Dept. of Physics, College of natural science, Kyunghee University)
[C-1-6]GaAs Nanocrystals Fabricated by Ga and As Ion Implantation
Y. Kanemitsu, S. Mimura, S. Okamoto, K. S. Min, H. A. Atwater(1.Graduate School of Materials Science, Nara Institute of Science and Technology, 2.Thomas J. Watson Laboratory of Applied Physics, California Institute of Technology)
[C-1-7]Quantum Confinement Effect in Self-Assembled, Nanometer Silicon Dots
S. A. Ding, M. Ikeda, M. Fukuda, S. Miyazaki, M. Hirose(1.Department of Electrical Engineering, Hiroshima University, 2.CREST, Japan Science and Technology Corporation (JST))
[C-2-1]Single-Electron Tunneling in Nanocrystalline Silicon
Shunri Oda, Amit Dutta, S-P. Lee, Y. Hayafune, S. Hara, K. Nishiguchi, B. J. Hinds, S. Hatatani(1.Research Center for Quantum Effect Electronics, Tokyo Institute of Technology)
[C-2-2]Gated Resonant Tunneling Structures with Buried Tungsten Grating Adjacent to Semiconductor Heterostructures
Michihiko Suhara, Lars-Erik Wernersson, Boel Gustafson, Niclas Carlsson, Werner Seifert, Lars Samuelson, Kazuhito Furuya(1.Research Center for Quantum Effect Electronics, Tokyo Institute of Technology, 2.Department of Solid State Physics, Lund University, 3.Department of Electrical and Electronic Engineering, Tokyo Institute of Technology)
[C-2-3]STM Nano-Lithography with SiO2 Mask
Nan Li, Tatsuo Yoshinobu, Hiroshi Iwasaki(1.The Institute of Scientific and Industrial Research, Osaka University)
[C-2-4]Fabrication of High-Resolution and High-Aspect-Ratio Pattering on a Stepped Substrate by Scanning Probe Lithography Using a Multilayer-Resist System
Masayoshi Ishibashi, Nami Sugita, Seiji Heike, Hiroshi Kajiyama, Tomihiro Hashizume(1.Advanced Research Laboratory, Hitachi, Ltd.)
[C-2-5]Formation of Size- and Position-Controlled Nanometer Size Pt Dots on GaAs and InP Substrates by Pulsed Electrochemical Depositon
Taketomo Sato, Chinami Kaneshiro, Hiroshi Okada, Hideki Hasegawa(1.Research Center for Interface Quantum Electronics (RCIQE) and Graduate School of Electronics and Information Engineering, Hokkaido University)
[D-1-1]RF Device Trends for Wireless Applications
Masahiro Muraguchi(1.NTT Wireless Systems Laboratories)
[D-1-2]Strain Engineering of Silicon-Based Heterostructures: Materials and Devices
J. L. Hoyt, K. Rim, T. O. Mitchell, D. V. Singh, J. F. Gibbons(1.Solid State Electronics Laboratory, Stanford University)
[D-1-3]RF Noise Study of Small Gate Width Si-MOSFETs up to 8GHz Application for Low Power Consumption
E. Morifuji, C. E. Biber, W. Bachtold, T. Ohguro, T. Yoshitomi, H. Kimijima, T. Morimoto, H. S. Momose, Y. Katsumata, H. Iwai(1.Toshiba Corporation, 2.Swiss Federal Institute of Technology (ETH))
[D-1-4]An Analog Integrated Circuit for Motion Detection Based on Biological Correlation Model
Masahiro Ohtani, Tetsuya Asai, Naoki Ohshima, Hiroo Yonezu(1.Department of Electrical and Electronic Engineering, Toyohashi University of Technology)
[D-2-1]Modeling and Characterization for Ultra Deep Submission CMOS Devices
Narain D. Arora(1.Simplex Solutions, Inc.)
[D-2-2]Noticeable Enhancement of Edge Effect in Short Channel Characteristics of Trench-Isolated MOSFETs
Toshiyuki Oishi, Katsuomi Shiozawa, Akihiko Furukawa, Yuji Abe, Yasunori Tokuda(1.Advanced Technology R&D Center, Mitsubishi Electric Corporation)
[D-2-3]Stress-Induced Device Degradation Due to Die-Attach Process after Area Bump Formation
Nobuhiro Shimoyama, Katsuyuki Machida, Masakazu Shimaya, Hakaru Kyuragi(1.NTT System Electronics Laboratories)
[D-2-4]Oxide Thickness Dependence of Hot Carrier Stress Induced Drain Leakage Current Degradation in Thin-Oxide n-MOSFET's
Tahui Wang, N. K. Zous, L. Y. Huang, C. K. Yeh, T. S. Chao(1.Department of Electronics Engineering, National Chiao-Tung University, 2.National Nano Devices Lab.)
[D-2-5]Enhanced-Mobility Deep Submicron Strained-Si n-MOSFETs
Kern Rim, Judy L. Hoyt, James F. Gibbons(1.Solid State Electronics Laboratory, Stanford University)
[D-2-6]Performance Considerations in Using High-k Dielectrics for Deep Sub-Micron MOSFETs
A. Inani, V. Ramgopal Rao, B. Cheng, M. Cao, P. V. Voorde, W. Greene, J. C. S. Woo(1.EE Department, University of California, 2.ULSI Research Laboratory, Hewlett-Packard Laboratories)
[LA-1]Buried Insulator Engineering for sub-0.05μm Fully-Depleted SOI-MOSFET to Reduce the Drain Induced Barrier Lowering
Risho Koh(1.Silicon systems research laboratory, NEC Corporation)
[LA-2]A Novel Shallow Trench Isolation with Mini-Spacer Technology
W. K. Yeh, Tony Lin, Coming Chen, S. W. Sun(1.United Microelectronics Corp., Technology Development Division)
[LA-3]Improvement of SiO2/4H-SiC Interface by Using High Temperature Hydrogen Annealing at 1000℃
Kenji Fukuda, Kiyoko Nagai, Toshihiro Sekigawa, Sadafumi Yoshida, Kazuo Arai, Masahito Yoshikawa(1.New Energy and Industrial Technology Development Organization, Electrotechnical Laboratory, 2.Japan Atomic Energy Research Institute)
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